armv8: layerscape: Update early MMU for DDR after initialization

[u-boot] / arch / arm / include / asm / arch-fsl-layerscape / cpu.h

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 4ea4aeaf4c238886da0d8389eba131ab539ec4e3..bcf3e3863e6f08e1dc39b1e4dc3f8ec1fff61fa2 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -115,7 +115,11 @@ static struct mm_region early_map[] = {
        },
        { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
          CONFIG_SYS_FSL_DRAM_SIZE1,
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
          PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+#else  /* Start with nGnRnE and PXN and UXN to prevent speculative access */
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
+#endif
          PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
        },
        /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
@@ -130,7 +134,7 @@ static struct mm_region early_map[] = {
        },
        { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
          CONFIG_SYS_FSL_DRAM_SIZE2,
-         PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
          PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
        },
 #elif defined(CONFIG_FSL_LSCH2)
@@ -158,12 +162,16 @@ static struct mm_region early_map[] = {
        },
        { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
          CONFIG_SYS_FSL_DRAM_SIZE1,
+#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
          PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+#else  /* Start with nGnRnE and PXN and UXN to prevent speculative access */
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
+#endif
          PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
        },
        { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
          CONFIG_SYS_FSL_DRAM_SIZE2,
-         PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+         PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_PXN | PTE_BLOCK_UXN |
          PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
        },
 #endif