imx: mx7: default enable MDIO open drain

[u-boot] / arch / arm / include / asm / arch-fsl-layerscape / immap_lsch2.h

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index d941437d63ca3250663d2cd058feb83151080001..21b803ff0fa9b65a1f81307b5c8ca6db68b2ec45 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -11,7 +11,8 @@
 
 #define CONFIG_SYS_IMMR                                0x01000000
 #define CONFIG_SYS_DCSRBAR                     0x20000000
-#define CONFIG_SYS_DCSR_DCFG_ADDR      (CONFIG_SYS_DCSRBAR + 0x00220000)
+#define CONFIG_SYS_DCSR_DCFG_ADDR      (CONFIG_SYS_DCSRBAR + 0x00140000)
+#define CONFIG_SYS_DCSR_COP_CCP_ADDR   (CONFIG_SYS_DCSRBAR + 0x02008040)
 
 #define CONFIG_SYS_FSL_DDR_ADDR                        (CONFIG_SYS_IMMR + 0x00080000)
 #define CONFIG_SYS_CCI400_ADDR                 (CONFIG_SYS_IMMR + 0x00180000)
@@ -30,15 +31,15 @@
 #define CONFIG_SYS_NS16550_COM2                        (CONFIG_SYS_IMMR + 0x011c0600)
 #define CONFIG_SYS_NS16550_COM3                        (CONFIG_SYS_IMMR + 0x011d0500)
 #define CONFIG_SYS_NS16550_COM4                        (CONFIG_SYS_IMMR + 0x011d0600)
-#define CONFIG_SYS_FSL_XHCI_USB1_ADDR          (CONFIG_SYS_IMMR + 0x01f00000)
-#define CONFIG_SYS_FSL_XHCI_USB2_ADDR          (CONFIG_SYS_IMMR + 0x02000000)
-#define CONFIG_SYS_FSL_XHCI_USB3_ADDR          (CONFIG_SYS_IMMR + 0x02100000)
+#define CONFIG_SYS_LS1043A_XHCI_USB1_ADDR      (CONFIG_SYS_IMMR + 0x01f00000)
+#define CONFIG_SYS_LS1043A_XHCI_USB2_ADDR      (CONFIG_SYS_IMMR + 0x02000000)
+#define CONFIG_SYS_LS1043A_XHCI_USB3_ADDR      (CONFIG_SYS_IMMR + 0x02100000)
 #define CONFIG_SYS_PCIE1_ADDR                  (CONFIG_SYS_IMMR + 0x2400000)
 #define CONFIG_SYS_PCIE2_ADDR                  (CONFIG_SYS_IMMR + 0x2500000)
 #define CONFIG_SYS_PCIE3_ADDR                  (CONFIG_SYS_IMMR + 0x2600000)
 #define CONFIG_SYS_FSL_SEC_ADDR                        (CONFIG_SYS_IMMR + 0x700000)
 #define CONFIG_SYS_FSL_JR0_ADDR                        (CONFIG_SYS_IMMR + 0x710000)
-#define CONFIG_SYS_SNVS_ADDR                   (CONFIG_SYS_IMMR + 0xe90000)
+#define CONFIG_SYS_SEC_MON_ADDR                        (CONFIG_SYS_IMMR + 0xe90000)
 #define CONFIG_SYS_SFP_ADDR                    (CONFIG_SYS_IMMR + 0xe80200)
 
 #define CONFIG_SYS_FSL_TIMER_ADDR              0x02b00000
@@ -60,6 +61,10 @@
 #define CONFIG_SYS_PCIE1_PHYS_ADDR             0x4000000000ULL
 #define CONFIG_SYS_PCIE2_PHYS_ADDR             0x4800000000ULL
 #define CONFIG_SYS_PCIE3_PHYS_ADDR             0x5000000000ULL
+/* LUT registers */
+#define PCIE_LUT_BASE                          0x10000
+#define PCIE_LUT_LCTRL0                                0x7F8
+#define PCIE_LUT_DBG                           0x7FC
 
 /* TZ Address Space Controller Definitions */
 #define TZASC1_BASE                    0x01100000      /* as per CCSR map. */