Merge git://git.denx.de/u-boot-mpc85xx

[u-boot] / arch / arm / include / asm / arch-fsl-layerscape / immap_lsch2.h

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 97136a011ecb265e5017394a114f0ca6c7a3aa5a..d684a077303618870423ca431e216b61abf85d45 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -60,7 +60,7 @@
 #define CONFIG_SYS_PCIE2_PHYS_ADDR             0x4800000000ULL
 #define CONFIG_SYS_PCIE3_PHYS_ADDR             0x5000000000ULL
 /* LUT registers */
-#ifdef CONFIG_LS1012A
+#ifdef CONFIG_ARCH_LS1012A
 #define PCIE_LUT_BASE                          0xC0000
 #else
 #define PCIE_LUT_BASE                          0x10000
@@ -120,7 +120,7 @@ CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
 #endif
 
 #ifndef CONFIG_SYS_CCSRBAR
-#define CONFIG_SYS_CCSRBAR             CONFIG_SYS_CCSRBAR_DEFAULT
+#define CONFIG_SYS_CCSRBAR             0x01000000
 #endif
 
 #ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
@@ -128,7 +128,7 @@ CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
 #endif
 
 #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW    CONFIG_SYS_CCSRBAR_DEFAULT
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW    0x01000000
 #endif
 
 #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
@@ -168,6 +168,8 @@ struct sys_info {
        (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
 
 /* Device Configuration and Pin Control */
+#define DCFG_DCSR_PORCR1               0x0
+
 struct ccsr_gur {
        u32     porsr1;         /* POR status 1 */
 #define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK      0xFF800000
@@ -228,6 +230,8 @@ struct ccsr_gur {
 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK   0x3f
 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK   0xffff0000
 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT  16
+#define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK   0x0000ffff
+#define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT  0
 #define RCW_SB_EN_REG_INDEX    7
 #define RCW_SB_EN_MASK         0x00200000
 
@@ -333,6 +337,8 @@ struct ccsr_gur {
 
 #define SCFG_SNPCNFGCR_SECRDSNP                0x80000000
 #define SCFG_SNPCNFGCR_SECWRSNP                0x40000000
+#define SCFG_SNPCNFGCR_SATARDSNP       0x00800000
+#define SCFG_SNPCNFGCR_SATAWRSNP       0x00400000
 
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {