aspeed: AST2500 Pinctrl Driver

[u-boot] / arch / arm / include / asm / arch-fsl-layerscape / immap_lsch3.h

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 9e6b5e3c194c54af25033555bd5a625bc6a0e724..80c421f71041372ce57d53a4feee0d2d02f068d4 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -180,9 +180,9 @@ struct ccsr_gur {
        u32     gpporcr3;
        u32     gpporcr4;
        u8      res_030[0x60-0x30];
-#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT     25
+#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT     2
 #define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK      0x1F
-#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT  20
+#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT  7
 #define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK   0x1F
        u32     dcfg_fusesr;    /* Fuse status register */
        u8      res_064[0x70-0x64];
@@ -230,10 +230,19 @@ struct ccsr_gur {
 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK   0x3f
 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18
 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK  0x3f
+
+#if defined(CONFIG_ARCH_LS2080A)
 #define        FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK   0x00FF0000
 #define        FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT  16
 #define        FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK   0xFF000000
 #define        FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT  24
+#define FSL_CHASSIS3_SRDS1_PRTCL_MASK  FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK
+#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT
+#define FSL_CHASSIS3_SRDS2_PRTCL_MASK  FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK
+#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
+#define FSL_CHASSIS3_SRDS1_REGSR       29
+#define FSL_CHASSIS3_SRDS2_REGSR       29
+#endif
 #define RCW_SB_EN_REG_INDEX    9
 #define RCW_SB_EN_MASK         0x00000400