omap-common: Common serial and usbethaddr functions based on die id

[u-boot] / arch / arm / include / asm / arch-fsl-lsch3 / config.h

diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index 8675e91fca07e260ea3a25fc729d778cc3e7772c..96d6c98cb8312c38606e740fcc288b13e4e5303a 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -10,6 +10,7 @@
 #include <fsl_ddrc_version.h>
 
 #define CONFIG_SYS_PAGE_SIZE           0x10000
+#define CONFIG_SYS_CACHELINE_SIZE      64
 
 #ifndef L1_CACHE_BYTES
 #define L1_CACHE_SHIFT         6
@@ -18,6 +19,7 @@
 
 #define CONFIG_MP
 #define CONFIG_SYS_FSL_OCRAM_BASE      0x18000000      /* initial RAM */
+#define CONFIG_SYS_FSL_OCRAM_SIZE      0x00200000      /* 2M */
 /* Link Definitions */
 #define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
 
@@ -63,6 +65,9 @@
 #define I2C3_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x01020000)
 #define I2C4_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x01030000)
 
+#define CONFIG_SYS_LS2085A_XHCI_USB1_ADDR      (CONFIG_SYS_IMMR + 0x02100000)
+#define CONFIG_SYS_LS2085A_XHCI_USB2_ADDR      (CONFIG_SYS_IMMR + 0x02110000)
+
 /* TZ Protection Controller Definitions */
 #define TZPC_BASE                              0x02200000
 #define TZPCR0SIZE_BASE                                (TZPC_BASE)
@@ -132,6 +137,17 @@
 #define CCI_MN_DVM_DOMAIN_CTL          0x200
 #define CCI_MN_DVM_DOMAIN_CTL_SET      0x210
 
+#define CCI_RN_I_0_BASE                        (CCI_MN_BASE + 0x800000)
+#define CCI_RN_I_2_BASE                        (CCI_MN_BASE + 0x820000)
+#define CCI_RN_I_6_BASE                        (CCI_MN_BASE + 0x860000)
+#define CCI_RN_I_12_BASE               (CCI_MN_BASE + 0x8C0000)
+#define CCI_RN_I_16_BASE               (CCI_MN_BASE + 0x900000)
+#define CCI_RN_I_20_BASE               (CCI_MN_BASE + 0x940000)
+
+#define CCI_S0_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x10)
+#define CCI_S1_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x110)
+#define CCI_S2_QOS_CONTROL_BASE(x) ((CCI_RN_I_0_BASE + (x * 0x10000)) + 0x210)
+
 /* Device Configuration */
 #define DCFG_BASE              0x01e00000
 #define DCFG_PORSR1                    0x000