Exynos542x: Add and enable get_periph_rate support

[u-boot] / arch / arm / include / asm / arch-keystone / clock-k2e.h

diff --git a/arch/arm/include/asm/arch-keystone/clock-k2e.h b/arch/arm/include/asm/arch-keystone/clock-k2e.h
index 41478110e5a7b28b7960ec4ee674b5cb782c1097..d013b830ed5c4243453ec3768a4497e90b660f28 100644 (file)
--- a/arch/arm/include/asm/arch-keystone/clock-k2e.h
+++ b/arch/arm/include/asm/arch-keystone/clock-k2e.h
@@ -25,27 +25,28 @@ enum ext_clk_e {
 
 extern unsigned int external_clk[ext_clk_count];
 
-enum clk_e {
-       core_pll_clk,
-       pass_pll_clk,
-       ddr3_pll_clk,
-       sys_clk0_clk,
-       sys_clk0_1_clk,
-       sys_clk0_2_clk,
-       sys_clk0_3_clk,
-       sys_clk0_4_clk,
-       sys_clk0_6_clk,
-       sys_clk0_8_clk,
-       sys_clk0_12_clk,
-       sys_clk0_24_clk,
-       sys_clk1_clk,
-       sys_clk1_3_clk,
-       sys_clk1_4_clk,
-       sys_clk1_6_clk,
-       sys_clk1_12_clk,
-       sys_clk2_clk,
-       sys_clk3_clk
-};
+#define CLK_LIST(CLK)\
+       CLK(0, core_pll_clk)\
+       CLK(1, pass_pll_clk)\
+       CLK(2, ddr3_pll_clk)\
+       CLK(3, sys_clk0_clk)\
+       CLK(4, sys_clk0_1_clk)\
+       CLK(5, sys_clk0_2_clk)\
+       CLK(6, sys_clk0_3_clk)\
+       CLK(7, sys_clk0_4_clk)\
+       CLK(8, sys_clk0_6_clk)\
+       CLK(9, sys_clk0_8_clk)\
+       CLK(10, sys_clk0_12_clk)\
+       CLK(11, sys_clk0_24_clk)\
+       CLK(12, sys_clk1_clk)\
+       CLK(13, sys_clk1_3_clk)\
+       CLK(14, sys_clk1_4_clk)\
+       CLK(15, sys_clk1_6_clk)\
+       CLK(16, sys_clk1_12_clk)\
+       CLK(17, sys_clk2_clk)\
+       CLK(18, sys_clk3_clk)
+
+#define PLLSET_CMD_LIST        "<pa|ddr3>"
 
 #define KS2_CLK1_6     sys_clk0_6_clk
 
@@ -56,10 +57,26 @@ enum pll_type_e {
        DDR3_PLL,
 };
 
+enum {
+       SPD800,
+       SPD850,
+       SPD1000,
+       SPD1250,
+       SPD1350,
+       SPD1400,
+       SPD1500,
+       SPD_RSV
+};
+
 #define CORE_PLL_800   {CORE_PLL, 16, 1, 2}
+#define CORE_PLL_850   {CORE_PLL, 17, 1, 2}
 #define CORE_PLL_1000  {CORE_PLL, 20, 1, 2}
 #define CORE_PLL_1200  {CORE_PLL, 24, 1, 2}
 #define PASS_PLL_1000  {PASS_PLL, 20, 1, 2}
+#define CORE_PLL_1250  {CORE_PLL, 25, 1, 2}
+#define CORE_PLL_1350  {CORE_PLL, 27, 1, 2}
+#define CORE_PLL_1400  {CORE_PLL, 28, 1, 2}
+#define CORE_PLL_1500  {CORE_PLL, 30, 1, 2}
 #define DDR3_PLL_200   {DDR3_PLL, 4,  1, 2}
 #define DDR3_PLL_400   {DDR3_PLL, 16, 1, 4}
 #define DDR3_PLL_800   {DDR3_PLL, 16, 1, 2}