Exynos542x: Add and enable get_periph_rate support

[u-boot] / arch / arm / include / asm / arch-keystone / hardware-k2hk.h

diff --git a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
index e7dff059b867edc959c4653d3b9fc6e99ede302c..195c0d300396dbed07898089595e676c761ee791 100644 (file)
--- a/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
+++ b/arch/arm/include/asm/arch-keystone/hardware-k2hk.h
@@ -10,46 +10,14 @@
 #ifndef __ASM_ARCH_HARDWARE_K2HK_H
 #define __ASM_ARCH_HARDWARE_K2HK_H
 
-#define KS2_PLL_CNTRL_BASE             0x02310000
-#define KS2_CLOCK_BASE                 KS2_PLL_CNTRL_BASE
-#define KS2_RSTCTRL                    (KS2_PLL_CNTRL_BASE + 0xe8)
-#define KS2_RSTCTRL_KEY                        0x5a69
-#define KS2_RSTCTRL_MASK               0xffff0000
-#define KS2_RSTCTRL_SWRST              0xfffe0000
-
-#define KS2_DEVICE_STATE_CTRL_BASE     0x02620000
-#define KS2_JTAG_ID_REG                        (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
-#define KS2_DEVSTAT                    (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
-
-#define KS2_MISC_CTRL                  (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
-
 #define KS2_ARM_PLL_EN                 BIT(13)
 
-#define KS2_SPI0_BASE                  0x21000400
-#define KS2_SPI1_BASE                  0x21000600
-#define KS2_SPI2_BASE                  0x21000800
-#define KS2_SPI_BASE                   KS2_SPI0_BASE
-
-/* Chip configuration unlock codes and registers */
-#define KS2_KICK0                      (KS2_DEVICE_STATE_CTRL_BASE + 0x38)
-#define KS2_KICK1                      (KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
-#define KS2_KICK0_MAGIC                        0x83e70b13
-#define KS2_KICK1_MAGIC                        0x95a4f1e0
-
 /* PA SS Registers */
 #define KS2_PASS_BASE                  0x02000000
 
 /* PLL control registers */
-#define KS2_MAINPLLCTL0                        (KS2_DEVICE_STATE_CTRL_BASE + 0x350)
-#define KS2_MAINPLLCTL1                        (KS2_DEVICE_STATE_CTRL_BASE + 0x354)
-#define KS2_PASSPLLCTL0                        (KS2_DEVICE_STATE_CTRL_BASE + 0x358)
-#define KS2_PASSPLLCTL1                        (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
-#define KS2_DDR3APLLCTL0               (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
-#define KS2_DDR3APLLCTL1               (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
 #define KS2_DDR3BPLLCTL0               (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
 #define KS2_DDR3BPLLCTL1               (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
-#define KS2_ARMPLLCTL0                 (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
-#define KS2_ARMPLLCTL1                 (KS2_DEVICE_STATE_CTRL_BASE + 0x374)
 
 /* Power and Sleep Controller (PSC) Domains */
 #define KS2_LPSC_MOD                   0
@@ -106,26 +74,33 @@
 #define KS2_LPSC_XGE                   50
 #define KS2_LPSC_ARM_SREFLEX           51
 
-/* DDR3A definitions */
-#define KS2_DDR3A_EMIF_CTRL_BASE       0x21010000
-#define KS2_DDR3A_EMIF_DATA_BASE       0x80000000
-#define KS2_DDR3A_DDRPHYC              0x02329000
 /* DDR3B definitions */
 #define KS2_DDR3B_EMIF_CTRL_BASE       0x21020000
 #define KS2_DDR3B_EMIF_DATA_BASE       0x60000000
 #define KS2_DDR3B_DDRPHYC              0x02328000
 
-/* Queue manager */
-#define KS2_QM_MANAGER_BASE            0x02a02000
-#define KS2_QM_DESC_SETUP_BASE         0x02a03000
-#define KS2_QM_MANAGER_QUEUES_BASEi    0x02a80000
-#define KS2_QM_MANAGER_Q_PROXY_BASE    0x02ac0000
-#define KS2_QM_QUEUE_STATUS_BASE       0x02a40000
+#define KS2_CIC2_DDR3_ECC_IRQ_NUM      0x0D3 /* DDR3 ECC system irq number */
+#define KS2_CIC2_DDR3_ECC_CHAN_NUM     0x01D /* DDR3 ECC int mapped to CIC2
+                                                channel 29 */
 
-/* MSMC control */
-#define KS2_MSMC_CTRL_BASE             0x0bc00000
+/* SGMII SerDes */
+#define KS2_LANES_PER_SGMII_SERDES     4
 
 /* Number of DSP cores */
 #define KS2_NUM_DSPS                   8
 
+/* NETCP pktdma */
+#define KS2_NETCP_PDMA_CTRL_BASE       0x02004000
+#define KS2_NETCP_PDMA_TX_BASE         0x02004400
+#define KS2_NETCP_PDMA_TX_CH_NUM       9
+#define KS2_NETCP_PDMA_RX_BASE         0x02004800
+#define KS2_NETCP_PDMA_RX_CH_NUM       26
+#define KS2_NETCP_PDMA_SCHED_BASE      0x02004c00
+#define KS2_NETCP_PDMA_RX_FLOW_BASE    0x02005000
+#define KS2_NETCP_PDMA_RX_FLOW_NUM     32
+#define KS2_NETCP_PDMA_TX_SND_QUEUE    648
+
+/* NETCP */
+#define KS2_NETCP_BASE                 0x02000000
+
 #endif /* __ASM_ARCH_HARDWARE_H */