ls102xa: fdt: Disable QSPI and DSPI in NOR/NAND/SD boot

[u-boot] / arch / arm / include / asm / arch-ls102xa / immap_ls102xa.h

diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index b0c267cfc2b2680e7bbe6c30e05297fa3dcd2e87..f70d568d467841784e77f4b89e8c9fef77038c42 100644 (file)
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -17,6 +17,9 @@
 #define SOC_VER_LS1021         0x11
 #define SOC_VER_LS1022         0x12
 
+#define CCSR_BRR_OFFSET                0xe4
+#define CCSR_SCRATCHRW1_OFFSET 0x200
+
 #define RCWSR0_SYS_PLL_RAT_SHIFT       25
 #define RCWSR0_SYS_PLL_RAT_MASK                0x1f
 #define RCWSR0_MEM_PLL_RAT_SHIFT       16
@@ -29,6 +32,11 @@
 #define ARCH_TIMER_CTRL_ENABLE         (1 << 0)
 #define SYS_COUNTER_CTRL_ENABLE                (1 << 24)
 
+#define DCFG_CCSR_PORSR1_RCW_MASK      0xff800000
+#define DCFG_CCSR_PORSR1_RCW_SRC_I2C   0x24800000
+
+#define DCFG_DCSR_PORCR1               0
+
 struct sys_info {
        unsigned long freq_processor[CONFIG_MAX_CPUS];
        unsigned long freq_systembus;
@@ -97,7 +105,10 @@ struct ccsr_gur {
 
 #define SCFG_ETSECDMAMCR_LE_BD_FR      0xf8001a0f
 #define SCFG_ETSECCMCR_GE2_CLK125      0x04000000
+#define SCFG_ETSECCMCR_GE0_CLK125      0x00000000
+#define SCFG_ETSECCMCR_GE1_CLK125      0x08000000
 #define SCFG_PIXCLKCR_PXCKEN           0x80000000
+#define SCFG_QSPI_CLKSEL               0xc0100000
 
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
@@ -447,6 +458,8 @@ struct ccsr_ddr {
 #define CCI400_CTRLORD_TERM_BARRIER    0x00000008
 #define CCI400_CTRLORD_EN_BARRIER      0
 #define CCI400_SHAORD_NON_SHAREABLE    0x00000002
+#define CCI400_DVM_MESSAGE_REQ_EN      0x00000002
+#define CCI400_SNOOP_REQ_EN            0x00000001
 
 /* CCI-400 registers */
 struct ccsr_cci400 {