SPDX: Convert all of our single license tags to Linux Kernel style

[u-boot] / arch / arm / include / asm / arch-meson / gxbb.h

diff --git a/arch/arm/include/asm/arch-meson/gxbb.h b/arch/arm/include/asm/arch-meson/gxbb.h
index f90f632dafec766950b74321fc59ba0a59ae030c..c7713b27b93f39470212bb3a69b1a49aa8c4a106 100644 (file)
--- a/arch/arm/include/asm/arch-meson/gxbb.h
+++ b/arch/arm/include/asm/arch-meson/gxbb.h
@@ -1,16 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __GXBB_H__
 #define __GXBB_H__
 
+#define GXBB_FIRMWARE_MEM_SIZE 0x1000000
+
+#define GXBB_AOBUS_BASE                0xc8100000
 #define GXBB_PERIPHS_BASE      0xc8834400
 #define GXBB_HIU_BASE          0xc883c000
 #define GXBB_ETH_BASE          0xc9410000
 
+/* Always-On Peripherals registers */
+#define GXBB_AO_ADDR(off)      (GXBB_AOBUS_BASE + ((off) << 2))
+
+#define GXBB_AO_SEC_GP_CFG0    GXBB_AO_ADDR(0x90)
+#define GXBB_AO_SEC_GP_CFG3    GXBB_AO_ADDR(0x93)
+#define GXBB_AO_SEC_GP_CFG4    GXBB_AO_ADDR(0x94)
+#define GXBB_AO_SEC_GP_CFG5    GXBB_AO_ADDR(0x95)
+
+#define GXBB_AO_MEM_SIZE_MASK  0xFFFF0000
+#define GXBB_AO_MEM_SIZE_SHIFT 16
+#define GXBB_AO_BL31_RSVMEM_SIZE_MASK  0xFFFF0000
+#define GXBB_AO_BL31_RSVMEM_SIZE_SHIFT 16
+#define GXBB_AO_BL32_RSVMEM_SIZE_MASK  0xFFFF
+
 /* Peripherals registers */
 #define GXBB_PERIPHS_ADDR(off) (GXBB_PERIPHS_BASE + ((off) << 2))
 
@@ -20,16 +36,16 @@
 #define GXBB_GPIO_IN(n)                GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 1)
 #define GXBB_GPIO_OUT(n)       GXBB_PERIPHS_ADDR(_GXBB_GPIO_OFF(n) + 2)
 
-/* Pinmux registers 0 to 12 */
-#define GXBB_PINMUX(n)         GXBB_PERIPHS_ADDR(0x2c + (n))
-
 #define GXBB_ETH_REG_0         GXBB_PERIPHS_ADDR(0x50)
 #define GXBB_ETH_REG_1         GXBB_PERIPHS_ADDR(0x51)
+#define GXBB_ETH_REG_2         GXBB_PERIPHS_ADDR(0x56)
+#define GXBB_ETH_REG_3         GXBB_PERIPHS_ADDR(0x57)
 
 #define GXBB_ETH_REG_0_PHY_INTF                BIT(0)
 #define GXBB_ETH_REG_0_TX_PHASE(x)     (((x) & 3) << 5)
 #define GXBB_ETH_REG_0_TX_RATIO(x)     (((x) & 7) << 7)
 #define GXBB_ETH_REG_0_PHY_CLK_EN      BIT(10)
+#define GXBB_ETH_REG_0_INVERT_RMII_CLK BIT(11)
 #define GXBB_ETH_REG_0_CLK_EN          BIT(12)
 
 /* HIU registers */
@@ -47,6 +63,7 @@
 #define GXBB_GCLK_MPEG_OTHER   GXBB_HIU_ADDR(0x53)
 #define GXBB_GCLK_MPEG_AO      GXBB_HIU_ADDR(0x54)
 
+#define GXBB_GCLK_MPEG_0_I2C   BIT(9)
 #define GXBB_GCLK_MPEG_1_ETH   BIT(3)
 
 #endif /* __GXBB_H__ */