Merge branch 'next' of git://git.denx.de/u-boot-net into next

[u-boot] / arch / arm / include / asm / arch-mx31 / imx-regs.h

diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h
index afdaa1ce6c46ccfbc37a766a2473a3d6d1d69243..7ddbbd627c1a3488ee1ec65d310c6979c8897765 100644 (file)
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -98,6 +98,12 @@ struct iim_regs {
        u32 iim_scs3;
 };
 
+struct iomuxc_regs {
+       u32 unused1;
+       u32 unused2;
+       u32 gpr;
+};
+
 struct mx3_cpu_type {
        u8 srev;
        u32 v;
@@ -594,6 +600,19 @@ struct esdc_regs {
 #define WEIM_ESDCFG1   0xB800100C
 #define WEIM_ESDMISC   0xB8001010
 
+#define UART1_BASE     0x43F90000
+#define UART2_BASE     0x43F94000
+#define UART3_BASE     0x5000C000
+#define UART4_BASE     0x43FB0000
+#define UART5_BASE     0x43FB4000
+
+#define I2C1_BASE_ADDR          0x43f80000
+#define I2C1_CLK_OFFSET                26
+#define I2C2_BASE_ADDR          0x43F98000
+#define I2C2_CLK_OFFSET                28
+#define I2C3_BASE_ADDR          0x43f84000
+#define I2C3_CLK_OFFSET                30
+
 #define ESDCTL_SDE                     (1 << 31)
 #define ESDCTL_CMD_RW                  (0 << 28)
 #define ESDCTL_CMD_PRECHARGE           (1 << 28)
@@ -636,7 +655,6 @@ struct esdc_regs {
 #define WEIM_BASE      0xb8002000
 
 #define IOMUXC_BASE    0x43FAC000
-#define IOMUXC_GPR     (IOMUXC_BASE + 0x8)
 #define IOMUXC_SW_MUX_CTL(x)   (IOMUXC_BASE + 0xc + (x) * 4)
 #define IOMUXC_SW_PAD_CTL(x)   (IOMUXC_BASE + 0x154 + (x) * 4)
 
@@ -698,6 +716,13 @@ struct esdc_regs {
 #define MUX_CTL_CSPI3_SPI_RDY  0x0e
 #define MUX_CTL_CSPI3_MOSI             0x13
 
+#define MUX_CTL_SD1_DATA1      0x18
+#define MUX_CTL_SD1_DATA2      0x19
+#define MUX_CTL_SD1_DATA3      0x1a
+#define MUX_CTL_SD1_CMD                0x1d
+#define MUX_CTL_SD1_CLK                0x1e
+#define MUX_CTL_SD1_DATA0      0x1f
+
 #define MUX_CTL_USBH2_DATA1    0x40
 #define MUX_CTL_USBH2_DIR      0x44
 #define MUX_CTL_USBH2_STP      0x45
@@ -844,6 +869,10 @@ struct esdc_regs {
  */
 #define NFC_BASE_ADDR  0xB8000000
 
+/* SD card controller */
+#define SDHC1_BASE_ADDR        0x50004000
+#define SDHC2_BASE_ADDR        0x50008000
+
 /*
  * Internal RAM (16KB)
  */
@@ -879,4 +908,31 @@ struct esdc_regs {
 #define MXC_EHCI_IPPUE_DOWN            (1 << 8)
 #define MXC_EHCI_IPPUE_UP              (1 << 9)
 
+/*
+ * CSPI register definitions
+ */
+#define MXC_CSPI
+#define MXC_CSPICTRL_EN                (1 << 0)
+#define MXC_CSPICTRL_MODE      (1 << 1)
+#define MXC_CSPICTRL_XCH       (1 << 2)
+#define MXC_CSPICTRL_SMC       (1 << 3)
+#define MXC_CSPICTRL_POL       (1 << 4)
+#define MXC_CSPICTRL_PHA       (1 << 5)
+#define MXC_CSPICTRL_SSCTL     (1 << 6)
+#define MXC_CSPICTRL_SSPOL     (1 << 7)
+#define MXC_CSPICTRL_CHIPSELECT(x)     (((x) & 0x3) << 24)
+#define MXC_CSPICTRL_BITCOUNT(x)       (((x) & 0x1f) << 8)
+#define MXC_CSPICTRL_DATARATE(x)       (((x) & 0x7) << 16)
+#define MXC_CSPICTRL_TC                (1 << 8)
+#define MXC_CSPICTRL_RXOVF     (1 << 6)
+#define MXC_CSPICTRL_MAXBITS   0x1f
+
+#define MXC_CSPIPERIOD_32KHZ   (1 << 15)
+#define MAX_SPI_BYTES  4
+
+#define MXC_SPI_BASE_ADDRESSES \
+       0x43fa4000, \
+       0x50010000, \
+       0x53f84000,
+
 #endif /* __ASM_ARCH_MX31_IMX_REGS_H */