#endif /* CONFIG_MX6Q */
#else
+enum {
+ DDR_TYPE_DDR3,
+ DDR_TYPE_LPDDR2,
+};
+
/* MMDC P0/P1 Registers */
struct mmdc_p_regs {
u32 mdctl;
u8 SRT; /* self-refresh temperature: 0=normal, 1=extended */
};
+/* Device Information: Varies per LPDDR2 part number and speed grade */
+struct mx6_lpddr2_cfg {
+ u16 mem_speed; /* ie 800 for LPDDR2-800 */
+ u8 density; /* chip density (Gb) (1,2,4,8) */
+ u8 width; /* bus width (bits) (4,8,16) */
+ u8 banks; /* number of banks */
+ u8 rowaddr; /* row address bits (11-16)*/
+ u8 coladdr; /* col address bits (9-12) */
+ u16 trcd_lp;
+ u16 trppb_lp;
+ u16 trpab_lp;
+ u16 trcmin; /* tRC min (ns*100) */
+ u16 trasmin; /* tRAS min (ns*100) */
+};
+
/* System Information: Varies per board design, layout, and term choices */
struct mx6_ddr_sysinfo {
u8 dsize; /* size of bus (in dwords: 0=16bit,1=32bit,2=64bit) */
u8 rst_to_cke; /* Time from SDE enable to CKE rise */
u8 sde_to_rst; /* Time from SDE enable until DDR reset# is high */
u8 pd_fast_exit;/* enable precharge powerdown fast-exit */
+ u8 ddr_type; /* DDR type: DDR3(0) or LPDDR2(1) */
+ u8 refsel; /* REF_SEL field of register MDREF */
+ u8 refr; /* REFR field of register MDREF */
};
/*
const struct mx6sl_iomux_ddr_regs *,
const struct mx6sl_iomux_grp_regs *);
+#if defined(CONFIG_MX6_DDRCAL)
+int mmdc_do_write_level_calibration(struct mx6_ddr_sysinfo const *sysinfo);
+int mmdc_do_dqs_calibration(struct mx6_ddr_sysinfo const *sysinfo);
+void mmdc_read_calibration(struct mx6_ddr_sysinfo const *sysinfo,
+ struct mx6_mmdc_calibration *calib);
+#endif
+
/* configure mx6 mmdc registers */
void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,
const struct mx6_mmdc_calibration *,
- const struct mx6_ddr3_cfg *);
+ const void *);
#endif /* CONFIG_SPL_BUILD */
#define MX6_MMDC_P0_MPDGCTRL1 0x021b0840
#define MX6_MMDC_P0_MPRDDLCTL 0x021b0848
#define MX6_MMDC_P0_MPWRDLCTL 0x021b0850
+#define MX6_MMDC_P0_MPZQLP2CTL 0x021b085C
#define MX6_MMDC_P0_MPMUR0 0x021b08b8
#define MX6_MMDC_P1_MDCTL 0x021b4000
#define MX6_MMDC_P1_MPDGCTRL1 0x021b4840
#define MX6_MMDC_P1_MPRDDLCTL 0x021b4848
#define MX6_MMDC_P1_MPWRDLCTL 0x021b4850
+#define MX6_MMDC_P1_MPZQLP2CTL 0x021b485C
#define MX6_MMDC_P1_MPMUR0 0x021b48b8
#endif /*__ASM_ARCH_MX6_DDR_H__ */