/*
* MXS DMA channels
*/
+#if defined(CONFIG_MX23)
+enum {
+ MXS_DMA_CHANNEL_AHB_APBH_LCDIF = 0,
+ MXS_DMA_CHANNEL_AHB_APBH_SSP0,
+ MXS_DMA_CHANNEL_AHB_APBH_SSP1,
+ MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
+ MXS_MAX_DMA_CHANNELS,
+};
+#elif defined(CONFIG_MX28)
enum {
MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0,
MXS_DMA_CHANNEL_AHB_APBH_SSP1,
MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
- MXS_DMA_CHANNEL_AHB_APBH_SSP,
+ MXS_DMA_CHANNEL_AHB_APBH_HSADC,
+ MXS_DMA_CHANNEL_AHB_APBH_LCDIF,
+ MXS_DMA_CHANNEL_AHB_APBH_RESERVED0,
+ MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
MXS_MAX_DMA_CHANNELS,
};
+#endif
/*
* MXS DMA hardware command.