Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

[u-boot] / arch / arm / include / asm / arch-mxs / regs-ssp.h

diff --git a/arch/arm/include/asm/arch-mxs/regs-ssp.h b/arch/arm/include/asm/arch-mxs/regs-ssp.h
index be71d48947716064ff96226fe3a64baf2550e538..5920f9b4dc7bf3b2a9daf82a610dbfe59b748c6b 100644 (file)
--- a/arch/arm/include/asm/arch-mxs/regs-ssp.h
+++ b/arch/arm/include/asm/arch-mxs/regs-ssp.h
@@ -28,30 +28,97 @@
 #include <asm/arch/regs-common.h>
 
 #ifndef        __ASSEMBLY__
-struct mx28_ssp_regs {
-       mx28_reg_32(hw_ssp_ctrl0)
-       mx28_reg_32(hw_ssp_cmd0)
-       mx28_reg_32(hw_ssp_cmd1)
-       mx28_reg_32(hw_ssp_xfer_size)
-       mx28_reg_32(hw_ssp_block_size)
-       mx28_reg_32(hw_ssp_compref)
-       mx28_reg_32(hw_ssp_compmask)
-       mx28_reg_32(hw_ssp_timing)
-       mx28_reg_32(hw_ssp_ctrl1)
-       mx28_reg_32(hw_ssp_data)
-       mx28_reg_32(hw_ssp_sdresp0)
-       mx28_reg_32(hw_ssp_sdresp1)
-       mx28_reg_32(hw_ssp_sdresp2)
-       mx28_reg_32(hw_ssp_sdresp3)
-       mx28_reg_32(hw_ssp_ddr_ctrl)
-       mx28_reg_32(hw_ssp_dll_ctrl)
-       mx28_reg_32(hw_ssp_status)
-       mx28_reg_32(hw_ssp_dll_sts)
-       mx28_reg_32(hw_ssp_debug)
-       mx28_reg_32(hw_ssp_version)
+#if defined(CONFIG_MX23)
+struct mxs_ssp_regs {
+       mxs_reg_32(hw_ssp_ctrl0)
+       mxs_reg_32(hw_ssp_cmd0)
+       mxs_reg_32(hw_ssp_cmd1)
+       mxs_reg_32(hw_ssp_compref)
+       mxs_reg_32(hw_ssp_compmask)
+       mxs_reg_32(hw_ssp_timing)
+       mxs_reg_32(hw_ssp_ctrl1)
+       mxs_reg_32(hw_ssp_data)
+       mxs_reg_32(hw_ssp_sdresp0)
+       mxs_reg_32(hw_ssp_sdresp1)
+       mxs_reg_32(hw_ssp_sdresp2)
+       mxs_reg_32(hw_ssp_sdresp3)
+       mxs_reg_32(hw_ssp_status)
+
+       uint32_t        reserved1[12];
+
+       mxs_reg_32(hw_ssp_debug)
+       mxs_reg_32(hw_ssp_version)
+};
+#elif defined(CONFIG_MX28)
+struct mxs_ssp_regs {
+       mxs_reg_32(hw_ssp_ctrl0)
+       mxs_reg_32(hw_ssp_cmd0)
+       mxs_reg_32(hw_ssp_cmd1)
+       mxs_reg_32(hw_ssp_xfer_size)
+       mxs_reg_32(hw_ssp_block_size)
+       mxs_reg_32(hw_ssp_compref)
+       mxs_reg_32(hw_ssp_compmask)
+       mxs_reg_32(hw_ssp_timing)
+       mxs_reg_32(hw_ssp_ctrl1)
+       mxs_reg_32(hw_ssp_data)
+       mxs_reg_32(hw_ssp_sdresp0)
+       mxs_reg_32(hw_ssp_sdresp1)
+       mxs_reg_32(hw_ssp_sdresp2)
+       mxs_reg_32(hw_ssp_sdresp3)
+       mxs_reg_32(hw_ssp_ddr_ctrl)
+       mxs_reg_32(hw_ssp_dll_ctrl)
+       mxs_reg_32(hw_ssp_status)
+       mxs_reg_32(hw_ssp_dll_sts)
+       mxs_reg_32(hw_ssp_debug)
+       mxs_reg_32(hw_ssp_version)
 };
 #endif
 
+static inline int mxs_ssp_bus_id_valid(int bus)
+{
+#if defined(CONFIG_MX23)
+       const unsigned int mxs_ssp_chan_count = 2;
+#elif defined(CONFIG_MX28)
+       const unsigned int mxs_ssp_chan_count = 4;
+#endif
+
+       if (bus >= mxs_ssp_chan_count)
+               return 0;
+
+       if (bus < 0)
+               return 0;
+
+       return 1;
+}
+
+static inline int mxs_ssp_clock_by_bus(unsigned int clock)
+{
+#if defined(CONFIG_MX23)
+       return 0;
+#elif defined(CONFIG_MX28)
+       return clock;
+#endif
+}
+
+static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port)
+{
+       switch (port) {
+       case 0:
+               return (struct mxs_ssp_regs *)MXS_SSP0_BASE;
+       case 1:
+               return (struct mxs_ssp_regs *)MXS_SSP1_BASE;
+#ifdef CONFIG_MX28
+       case 2:
+               return (struct mxs_ssp_regs *)MXS_SSP2_BASE;
+       case 3:
+               return (struct mxs_ssp_regs *)MXS_SSP3_BASE;
+#endif
+       default:
+               return NULL;
+       }
+}
+#endif
+
 #define        SSP_CTRL0_SFTRST                        (1 << 31)
 #define        SSP_CTRL0_CLKGATE                       (1 << 30)
 #define        SSP_CTRL0_RUN                           (1 << 29)
@@ -72,6 +139,11 @@ struct mx28_ssp_regs {
 #define        SSP_CTRL0_GET_RESP                      (1 << 17)
 #define        SSP_CTRL0_ENABLE                        (1 << 16)
 
+#ifdef CONFIG_MX23
+#define        SSP_CTRL0_XFER_COUNT_OFFSET             0
+#define        SSP_CTRL0_XFER_COUNT_MASK               0xffff
+#endif
+
 #define        SSP_CMD0_SOFT_TERMINATE                 (1 << 26)
 #define        SSP_CMD0_DBL_DATA_RATE_EN               (1 << 25)
 #define        SSP_CMD0_PRIM_BOOT_OP_EN                (1 << 24)
@@ -79,6 +151,12 @@ struct mx28_ssp_regs {
 #define        SSP_CMD0_SLOW_CLKING_EN                 (1 << 22)
 #define        SSP_CMD0_CONT_CLKING_EN                 (1 << 21)
 #define        SSP_CMD0_APPEND_8CYC                    (1 << 20)
+#if defined(CONFIG_MX23)
+#define        SSP_CMD0_BLOCK_SIZE_MASK                (0xf << 16)
+#define        SSP_CMD0_BLOCK_SIZE_OFFSET              16
+#define        SSP_CMD0_BLOCK_COUNT_MASK               (0xff << 8)
+#define        SSP_CMD0_BLOCK_COUNT_OFFSET             8
+#endif
 #define        SSP_CMD0_CMD_MASK                       0xff
 #define        SSP_CMD0_CMD_OFFSET                     0
 #define        SSP_CMD0_CMD_MMC_GO_IDLE_STATE          0x00
@@ -152,6 +230,7 @@ struct mx28_ssp_regs {
 #define        SSP_CMD1_CMD_ARG_MASK                   0xffffffff
 #define        SSP_CMD1_CMD_ARG_OFFSET                 0
 
+#if defined(CONFIG_MX28)
 #define        SSP_XFER_SIZE_XFER_COUNT_MASK           0xffffffff
 #define        SSP_XFER_SIZE_XFER_COUNT_OFFSET         0
 
@@ -159,6 +238,7 @@ struct mx28_ssp_regs {
 #define        SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET       4
 #define        SSP_BLOCK_SIZE_BLOCK_SIZE_MASK          0xf
 #define        SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET        0
+#endif
 
 #define        SSP_COMPREF_REFERENCE_MASK              0xffffffff
 #define        SSP_COMPREF_REFERENCE_OFFSET            0