ARM: mxs: move spl data

[u-boot] / arch / arm / include / asm / arch-mxs / sys_proto.h

diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h
index 43c7dd6bf10e7c274c3272cbae112daf47b45bef..b23ee6d88768f1ff9612dcc5cf0d2c1892e198fb 100644 (file)
--- a/arch/arm/include/asm/arch-mxs/sys_proto.h
+++ b/arch/arm/include/asm/arch-mxs/sys_proto.h
@@ -7,16 +7,10 @@
  * SPDX-License-Identifier:    GPL-2.0+
  */
 
-#ifndef __SYS_PROTO_H__
-#define __SYS_PROTO_H__
+#ifndef __MXS_SYS_PROTO_H__
+#define __MXS_SYS_PROTO_H__
 
-int mxs_reset_block(struct mxs_register_32 *reg);
-int mxs_wait_mask_set(struct mxs_register_32 *reg,
-                      uint32_t mask,
-                      unsigned int timeout);
-int mxs_wait_mask_clr(struct mxs_register_32 *reg,
-                      uint32_t mask,
-                      unsigned int timeout);
+#include <asm/mach-imx/sys_proto.h>
 
 int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int));
 
@@ -31,6 +25,8 @@ int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int));
 void mxs_common_spl_init(const uint32_t arg, const uint32_t *resptr,
                         const iomux_cfg_t *iomux_setup,
                         const unsigned int iomux_size);
+
+void mxs_power_switch_dcdc_clocksource(uint32_t freqsel);
 #endif
 
 struct mxs_pair {
@@ -46,6 +42,7 @@ static const struct mxs_pair mxs_boot_modes[] = {
        { 0x02, 0x1f, "SSP SPI #1, master, NOR" },
        { 0x03, 0x1f, "SSP SPI #2, master, NOR" },
        { 0x04, 0x1f, "NAND" },
+       { 0x06, 0x1f, "JTAG" },
        { 0x08, 0x1f, "SSP SPI #3, master, EEPROM" },
        { 0x09, 0x1f, "SSP SD/MMC #0" },
        { 0x0a, 0x1f, "SSP SD/MMC #1" },
@@ -60,6 +57,7 @@ static const struct mxs_pair mxs_boot_modes[] = {
        { 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" },
        { 0x04, 0x1f, "NAND, 3V3" },
        { 0x14, 0x1f, "NAND, 1V8" },
+       { 0x06, 0x1f, "JTAG" },
        { 0x08, 0x1f, "SSP SPI #3, master, 3V3 EEPROM" },
        { 0x18, 0x1f, "SSP SPI #3, master, 1V8 EEPROM" },
        { 0x09, 0x1f, "SSP SD/MMC #0, 3V3" },
@@ -70,6 +68,25 @@ static const struct mxs_pair mxs_boot_modes[] = {
 #endif
 };
 
+#define MXS_BM_USB                     0x00
+#define MXS_BM_I2C_MASTER_3V3          0x01
+#define MXS_BM_I2C_MASTER_1V8          0x11
+#define MXS_BM_SPI2_MASTER_3V3_NOR     0x02
+#define MXS_BM_SPI2_MASTER_1V8_NOR     0x12
+#define MXS_BM_SPI3_MASTER_3V3_NOR     0x03
+#define MXS_BM_SPI3_MASTER_1V8_NOR     0x13
+#define MXS_BM_NAND_3V3                        0x04
+#define MXS_BM_NAND_1V8                        0x14
+#define MXS_BM_JTAG                    0x06
+#define MXS_BM_SPI3_MASTER_3V3_EEPROM  0x08
+#define MXS_BM_SPI3_MASTER_1V8_EEPROM  0x18
+#define MXS_BM_SDMMC0_3V3              0x09
+#define MXS_BM_SDMMC0_1V8              0x19
+#define MXS_BM_SDMMC1_3V3              0x0a
+#define MXS_BM_SDMMC1_1V8              0x1a
+
+#define MXS_SPL_DATA ((struct mxs_spl_data *)(CONFIG_SYS_TEXT_BASE - 0x200))
+
 struct mxs_spl_data {
        uint8_t         boot_mode_idx;
        uint32_t        mem_dram_size;