#define SDP_SDRC_DLLAB_CTRL ((DLL_ENADLL << 3) | \
(DLL_LOCKDLL << 2) | (DLL_DLLPHASE_90 << 1))
-/* Infineon part of 3430SDP (165MHz optimized) 6.06ns
- * ACTIMA
- * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
- * TDPL (Twr) = 15/6 = 2.5 -> 3
- * TRRD = 12/6 = 2
- * TRCD = 18/6 = 3
- * TRP = 18/6 = 3
- * TRAS = 42/6 = 7
- * TRC = 60/6 = 10
- * TRFC = 72/6 = 12
- * ACTIMB
- * TCKE = 2
- * XSR = 120/6 = 20
- */
-#define INFINEON_TDAL_165 6
-#define INFINEON_TDPL_165 3
-#define INFINEON_TRRD_165 2
-#define INFINEON_TRCD_165 3
-#define INFINEON_TRP_165 3
-#define INFINEON_TRAS_165 7
-#define INFINEON_TRC_165 10
-#define INFINEON_TRFC_165 12
-#define INFINEON_V_ACTIMA_165 ((INFINEON_TRFC_165 << 27) | \
- (INFINEON_TRC_165 << 22) | (INFINEON_TRAS_165 << 18) | \
- (INFINEON_TRP_165 << 15) | (INFINEON_TRCD_165 << 12) | \
- (INFINEON_TRRD_165 << 9) | (INFINEON_TDPL_165 << 6) | \
- (INFINEON_TDAL_165))
+/* Helper macros to arrive at value of the SDRC_ACTIM_CTRLA register. */
+#define ACTIM_CTRLA_TRFC(v) (((v) & 0x1F) << 27) /* 31:27 */
+#define ACTIM_CTRLA_TRC(v) (((v) & 0x1F) << 22) /* 26:22 */
+#define ACTIM_CTRLA_TRAS(v) (((v) & 0x0F) << 18) /* 21:18 */
+#define ACTIM_CTRLA_TRP(v) (((v) & 0x07) << 15) /* 17:15 */
+#define ACTIM_CTRLA_TRCD(v) (((v) & 0x07) << 12) /* 14:12 */
+#define ACTIM_CTRLA_TRRD(v) (((v) & 0x07) << 9) /* 11:9 */
+#define ACTIM_CTRLA_TDPL(v) (((v) & 0x07) << 6) /* 8:6 */
+#define ACTIM_CTRLA_TDAL(v) (v & 0x1F) /* 4:0 */
+
+#define ACTIM_CTRLA(a,b,c,d,e,f,g,h) \
+ ACTIM_CTRLA_TRFC(a) | \
+ ACTIM_CTRLA_TRC(b) | \
+ ACTIM_CTRLA_TRAS(b) | \
+ ACTIM_CTRLA_TRP(d) | \
+ ACTIM_CTRLA_TRCD(e) | \
+ ACTIM_CTRLA_TRRD(f) | \
+ ACTIM_CTRLA_TDPL(g) | \
+ ACTIM_CTRLA_TDAL(h)
+
+/* Helper macros to arrive at value of the SDRC_ACTIM_CTRLB register. */
+#define ACTIM_CTRLB_TWTR(v) (((v) & 0x03) << 16) /* 17:16 */
+#define ACTIM_CTRLB_TCKE(v) (((v) & 0x07) << 12) /* 14:12 */
+#define ACTIM_CTRLB_TXP(v) (((v) & 0x07) << 8) /* 10:8 */
+#define ACTIM_CTRLB_TXSR(v) (v & 0xFF) /* 7:0 */
+
+#define ACTIM_CTRLB(a,b,c,d) \
+ ACTIM_CTRLB_TWTR(a) | \
+ ACTIM_CTRLB_TCKE(b) | \
+ ACTIM_CTRLB_TXP(b) | \
+ ACTIM_CTRLB_TXSR(d)
+
+/* Infineon part of 3430SDP (165MHz optimized) 6.06ns */
+#define INFINEON_TDAL_165 6 /* Twr/Tck + Trp/tck */
+ /* 15/6 + 18/6 = 5.5 -> 6 */
+#define INFINEON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */
+#define INFINEON_TRRD_165 2 /* 12/6 = 2 */
+#define INFINEON_TRCD_165 3 /* 18/6 = 3 */
+#define INFINEON_TRP_165 3 /* 18/6 = 3 */
+#define INFINEON_TRAS_165 7 /* 42/6 = 7 */
+#define INFINEON_TRC_165 10 /* 60/6 = 10 */
+#define INFINEON_TRFC_165 12 /* 72/6 = 12 */
+
+#define INFINEON_V_ACTIMA_165 \
+ ACTIM_CTRLA(INFINEON_TRFC_165, INFINEON_TRC_165, \
+ INFINEON_TRAS_165, INFINEON_TRP_165, \
+ INFINEON_TRCD_165, INFINEON_TRRD_165, \
+ INFINEON_TDPL_165, INFINEON_TDAL_165)
#define INFINEON_TWTR_165 1
#define INFINEON_TCKE_165 2
#define INFINEON_TXP_165 2
-#define INFINEON_XSR_165 20
-#define INFINEON_V_ACTIMB_165 ((INFINEON_TCKE_165 << 12) | \
- (INFINEON_XSR_165 << 0) | (INFINEON_TXP_165 << 8) | \
- (INFINEON_TWTR_165 << 16))
-
-/* Micron part of 3430 EVM (165MHz optimized) 6.06ns
- * ACTIMA
- * TDAL = Twr/Tck + Trp/tck= 15/6 + 18 /6 = 2.5 + 3 = 5.5 -> 6
- * TDPL (Twr) = 15/6 = 2.5 -> 3
- * TRRD = 12/6 = 2
- * TRCD = 18/6 = 3
- * TRP = 18/6 = 3
- * TRAS = 42/6 = 7
- * TRC = 60/6 = 10
- * TRFC = 125/6 = 21
- * ACTIMB
- * TWTR = 1
- * TCKE = 1
- * TXSR = 138/6 = 23
- * TXP = 25/6 = 4.1 ~5
- */
-#define MICRON_TDAL_165 6
-#define MICRON_TDPL_165 3
-#define MICRON_TRRD_165 2
-#define MICRON_TRCD_165 3
-#define MICRON_TRP_165 3
-#define MICRON_TRAS_165 7
-#define MICRON_TRC_165 10
-#define MICRON_TRFC_165 21
-#define MICRON_V_ACTIMA_165 ((MICRON_TRFC_165 << 27) | \
- (MICRON_TRC_165 << 22) | (MICRON_TRAS_165 << 18) | \
- (MICRON_TRP_165 << 15) | (MICRON_TRCD_165 << 12) | \
- (MICRON_TRRD_165 << 9) | (MICRON_TDPL_165 << 6) | \
- (MICRON_TDAL_165))
+#define INFINEON_XSR_165 20 /* 120/6 = 20 */
+
+#define INFINEON_V_ACTIMB_165 \
+ ACTIM_CTRLB(INFINEON_TWTR_165, INFINEON_TCKE_165, \
+ INFINEON_TXP_165, INFINEON_XSR_165)
+
+/* Micron part of 3430 EVM (165MHz optimized) 6.06ns */
+#define MICRON_TDAL_165 6 /* Twr/Tck + Trp/tck */
+ /* 15/6 + 18/6 = 5.5 -> 6 */
+#define MICRON_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */
+#define MICRON_TRRD_165 2 /* 12/6 = 2 */
+#define MICRON_TRCD_165 3 /* 18/6 = 3 */
+#define MICRON_TRP_165 3 /* 18/6 = 3 */
+#define MICRON_TRAS_165 7 /* 42/6 = 7 */
+#define MICRON_TRC_165 10 /* 60/6 = 10 */
+#define MICRON_TRFC_165 21 /* 125/6 = 21 */
+
+#define MICRON_V_ACTIMA_165 \
+ ACTIM_CTRLA(MICRON_TRFC_165, MICRON_TRC_165, \
+ MICRON_TRAS_165, MICRON_TRP_165, \
+ MICRON_TRCD_165, MICRON_TRRD_165, \
+ MICRON_TDPL_165, MICRON_TDAL_165)
#define MICRON_TWTR_165 1
#define MICRON_TCKE_165 1
-#define MICRON_XSR_165 23
-#define MICRON_TXP_165 5
-#define MICRON_V_ACTIMB_165 ((MICRON_TCKE_165 << 12) | \
- (MICRON_XSR_165 << 0) | (MICRON_TXP_165 << 8) | \
- (MICRON_TWTR_165 << 16))
-
-/*
- * NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns
- * ACTIMA
- * TDAL = Twr/Tck + Trp/tck = 15/6 + 18/6 = 2.5 + 3 = 5.5 -> 6
- * TDPL (Twr) = 15/6 = 2.5 -> 3
- * TRRD = 12/6 = 2
- * TRCD = 22.5/6 = 3.75 -> 4
- * TRP = 18/6 = 3
- * TRAS = 42/6 = 7
- * TRC = 60/6 = 10
- * TRFC = 140/6 = 23.3 -> 24
- * ACTIMB
- * TWTR = 2
- * TCKE = 2
- * TXSR = 200/6 = 33.3 -> 34
- * TXP = 1.0 + 1.1 = 2.1 -> 3
- */
-#define NUMONYX_TDAL_165 6
-#define NUMONYX_TDPL_165 3
-#define NUMONYX_TRRD_165 2
-#define NUMONYX_TRCD_165 4
-#define NUMONYX_TRP_165 3
-#define NUMONYX_TRAS_165 7
-#define NUMONYX_TRC_165 10
-#define NUMONYX_TRFC_165 24
-#define NUMONYX_V_ACTIMA_165 ((NUMONYX_TRFC_165 << 27) | \
- (NUMONYX_TRC_165 << 22) | (NUMONYX_TRAS_165 << 18) | \
- (NUMONYX_TRP_165 << 15) | (NUMONYX_TRCD_165 << 12) | \
- (NUMONYX_TRRD_165 << 9) | (NUMONYX_TDPL_165 << 6) | \
- (NUMONYX_TDAL_165))
-
-#define NUMONYX_TWTR_165 2
-#define NUMONYX_TCKE_165 2
-#define NUMONYX_TXP_165 3
-#define NUMONYX_XSR_165 34
-#define NUMONYX_V_ACTIMB_165 ((NUMONYX_TCKE_165 << 12) | \
- (NUMONYX_XSR_165 << 0) | (NUMONYX_TXP_165 << 8) | \
- (NUMONYX_TWTR_165 << 16))
+#define MICRON_XSR_165 23 /* 138/6 = 23 */
+#define MICRON_TXP_165 5 /* 25/6 = 4.1 => ~5 */
+
+#define MICRON_V_ACTIMB_165 \
+ ACTIM_CTRLB(MICRON_TWTR_165, MICRON_TCKE_165, \
+ MICRON_TXP_165, MICRON_XSR_165)
+
+#define MICRON_RAMTYPE 0x1
+#define MICRON_DDRTYPE 0x0
+#define MICRON_DEEPPD 0x1
+#define MICRON_B32NOT16 0x1
+#define MICRON_BANKALLOCATION 0x2
+#define MICRON_RAMSIZE ((PHYS_SDRAM_1_SIZE/(1024*1024))/2)
+#define MICRON_ADDRMUXLEGACY 0x1
+#define MICRON_CASWIDTH 0x5
+#define MICRON_RASWIDTH 0x2
+#define MICRON_LOCKSTATUS 0x0
+#define MICRON_V_MCFG ((MICRON_LOCKSTATUS << 30) | (MICRON_RASWIDTH << 24) | \
+ (MICRON_CASWIDTH << 20) | (MICRON_ADDRMUXLEGACY << 19) | \
+ (MICRON_RAMSIZE << 8) | (MICRON_BANKALLOCATION << 6) | \
+ (MICRON_B32NOT16 << 4) | (MICRON_DEEPPD << 3) | \
+ (MICRON_DDRTYPE << 2) | (MICRON_RAMTYPE))
+
+#define MICRON_ARCV 2030
+#define MICRON_ARE 0x1
+#define MICRON_V_RFR_CTRL ((MICRON_ARCV << 8) | (MICRON_ARE))
+
+#define MICRON_BL 0x2
+#define MICRON_SIL 0x0
+#define MICRON_CASL 0x3
+#define MICRON_WBST 0x0
+#define MICRON_V_MR ((MICRON_WBST << 9) | (MICRON_CASL << 4) | \
+ (MICRON_SIL << 3) | (MICRON_BL))
+
+/* NUMONYX part of IGEP v2 (165MHz optimized) 6.06ns */
+#define NUMONYX_TDAL_165 6 /* Twr/Tck + Trp/tck */
+ /* 15/6 + 18/6 = 5.5 -> 6 */
+#define NUMONYX_TDPL_165 3 /* 15/6 = 2.5 -> 3 (Twr) */
+#define NUMONYX_TRRD_165 2 /* 12/6 = 2 */
+#define NUMONYX_TRCD_165 4 /* 22.5/6 = 3.75 -> 4 */
+#define NUMONYX_TRP_165 3 /* 18/6 = 3 */
+#define NUMONYX_TRAS_165 7 /* 42/6 = 7 */
+#define NUMONYX_TRC_165 10 /* 60/6 = 10 */
+#define NUMONYX_TRFC_165 24 /* 140/6 = 23.3 -> 24 */
+
+#define NUMONYX_V_ACTIMA_165 \
+ ACTIM_CTRLA(NUMONYX_TRFC_165, NUMONYX_TRC_165, \
+ NUMONYX_TRAS_165, NUMONYX_TRP_165, \
+ NUMONYX_TRCD_165, NUMONYX_TRRD_165, \
+ NUMONYX_TDPL_165, NUMONYX_TDAL_165)
+
+#define NUMONYX_TWTR_165 2
+#define NUMONYX_TCKE_165 2
+#define NUMONYX_TXP_165 3 /* 200/6 = 33.3 -> 34 */
+#define NUMONYX_XSR_165 34 /* 1.0 + 1.1 = 2.1 -> 3 */
+
+#define NUMONYX_V_ACTIMB_165 \
+ ACTIM_CTRLB(NUMONYX_TWTR_165, NUMONYX_TCKE_165, \
+ NUMONYX_TXP_165, NUMONYX_XSR_165)
#ifdef CONFIG_OMAP3_INFINEON_DDR
-#define V_ACTIMA_165 INFINEON_V_ACTIMA_165
-#define V_ACTIMB_165 INFINEON_V_ACTIMB_165
+#define V_ACTIMA_165 INFINEON_V_ACTIMA_165
+#define V_ACTIMB_165 INFINEON_V_ACTIMB_165
#endif
+
#ifdef CONFIG_OMAP3_MICRON_DDR
-#define V_ACTIMA_165 MICRON_V_ACTIMA_165
-#define V_ACTIMB_165 MICRON_V_ACTIMB_165
+#define V_ACTIMA_165 MICRON_V_ACTIMA_165
+#define V_ACTIMB_165 MICRON_V_ACTIMB_165
+#define V_MCFG MICRON_V_MCFG
+#define V_RFR_CTRL MICRON_V_RFR_CTRL
+#define V_MR MICRON_V_MR
#endif
+
#ifdef CONFIG_OMAP3_NUMONYX_DDR
-#define V_ACTIMA_165 NUMONYX_V_ACTIMA_165
-#define V_ACTIMB_165 NUMONYX_V_ACTIMB_165
+#define V_ACTIMA_165 NUMONYX_V_ACTIMA_165
+#define V_ACTIMB_165 NUMONYX_V_ACTIMB_165
#endif
#if !defined(V_ACTIMA_165) || !defined(V_ACTIMB_165)
#error "Please choose the right DDR type in config header"
#endif
+#if defined(CONFIG_SPL_BUILD) && (!defined(V_MCFG) || !defined(V_RFR_CTRL))
+#error "Please choose the right DDR type in config header"
+#endif
+
/*
* GPMC settings -
* Definitions is as per the following format