Merge http://git.denx.de/u-boot-sunxi

[u-boot] / arch / arm / include / asm / arch-omap3 / mux.h

diff --git a/arch/arm/include/asm/arch-omap3/mux.h b/arch/arm/include/asm/arch-omap3/mux.h
index 0c01c731658d8b070bbb44c22fb73fd48b13e42d..2f8320629be86380876b7eada7a955dc7d403be7 100644 (file)
--- a/arch/arm/include/asm/arch-omap3/mux.h
+++ b/arch/arm/include/asm/arch-omap3/mux.h
@@ -3,20 +3,7 @@
  * Texas Instruments, <www.ti.com>
  * Syed Mohammed Khasim <x0khasim@ti.com>
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 #ifndef _MUX_H_
 #define _MUX_H_
@@ -404,6 +391,58 @@
 #define CONTROL_PADCONF_SDRC_CKE0      0x0262
 #define CONTROL_PADCONF_SDRC_CKE1      0x0264
 
+/* AM3517 specific mux configuration */
+#define CONTROL_PADCONF_SYS_NRESWARM   0x0A08
+/* CCDC */
+#define CONTROL_PADCONF_CCDC_PCLK      0x01E4
+#define CONTROL_PADCONF_CCDC_FIELD     0x01E6
+#define CONTROL_PADCONF_CCDC_HD                0x01E8
+#define CONTROL_PADCONF_CCDC_VD                0x01EA
+#define CONTROL_PADCONF_CCDC_WEN       0x01EC
+#define CONTROL_PADCONF_CCDC_DATA0     0x01EE
+#define CONTROL_PADCONF_CCDC_DATA1     0x01F0
+#define CONTROL_PADCONF_CCDC_DATA2     0x01F2
+#define CONTROL_PADCONF_CCDC_DATA3     0x01F4
+#define CONTROL_PADCONF_CCDC_DATA4     0x01F6
+#define CONTROL_PADCONF_CCDC_DATA5     0x01F8
+#define CONTROL_PADCONF_CCDC_DATA6     0x01FA
+#define CONTROL_PADCONF_CCDC_DATA7     0x01FC
+/* RMII */
+#define CONTROL_PADCONF_RMII_MDIO_DATA 0x01FE
+#define CONTROL_PADCONF_RMII_MDIO_CLK  0x0200
+#define CONTROL_PADCONF_RMII_RXD0      0x0202
+#define CONTROL_PADCONF_RMII_RXD1      0x0204
+#define CONTROL_PADCONF_RMII_CRS_DV    0x0206
+#define CONTROL_PADCONF_RMII_RXER      0x0208
+#define CONTROL_PADCONF_RMII_TXD0      0x020A
+#define CONTROL_PADCONF_RMII_TXD1      0x020C
+#define CONTROL_PADCONF_RMII_TXEN      0x020E
+#define CONTROL_PADCONF_RMII_50MHZ_CLK 0x0210
+#define CONTROL_PADCONF_USB0_DRVBUS    0x0212
+/* CAN */
+#define CONTROL_PADCONF_HECC1_TXD      0x0214
+#define CONTROL_PADCONF_HECC1_RXD      0x0216
+
+#define CONTROL_PADCONF_SYS_BOOT7      0x0218
+#define CONTROL_PADCONF_SDRC_DQS0N     0x021A
+#define CONTROL_PADCONF_SDRC_DQS1N     0x021C
+#define CONTROL_PADCONF_SDRC_DQS2N     0x021E
+#define CONTROL_PADCONF_SDRC_DQS3N     0x0220
+#define CONTROL_PADCONF_STRBEN_DLY0    0x0222
+#define CONTROL_PADCONF_STRBEN_DLY1    0x0224
+#define CONTROL_PADCONF_SYS_BOOT8      0x0226
+
+/* AM/DM37xx specific */
+#define CONTROL_PADCONF_GPIO127                0x0A54
+#define CONTROL_PADCONF_GPIO126                0x0A56
+#define CONTROL_PADCONF_GPIO128                0x0A58
+#define CONTROL_PADCONF_GPIO129                0x0A5A
+
+/* AM/DM37xx specific: gpio_127, gpio_127 and gpio_129 require configuration
+ * of the extended drain cells */
+#define OMAP34XX_CTRL_WKUP_CTRL                (OMAP34XX_CTRL_BASE + 0x0A5C)
+#define OMAP34XX_CTRL_WKUP_CTRL_GPIO_IO_PWRDNZ (1<<6)
+
 #define MUX_VAL(OFFSET,VALUE)\
        writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));