Merge branch 'master' of git://git.denx.de/u-boot-arm

[u-boot] / arch / arm / include / asm / arch-omap4 / clocks.h

diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h
index 37bdceebedd3d12061e5b8fa8dad68de45568cf4..45c947d648fe676119abdc18a068158aa9eef6dd 100644 (file)
--- a/arch/arm/include/asm/arch-omap4/clocks.h
+++ b/arch/arm/include/asm/arch-omap4/clocks.h
@@ -105,9 +105,11 @@ struct omap4_prcm_regs {
        u32 cm_ssc_deltamstep_dpll_ddrphy;
        u32 pad014[5];
        u32 cm_shadow_freq_config1;
+       u32 pad0141[47];
+       u32 cm_mpu_mpu_clkctrl;
 
        /* cm1.dsp */
-       u32 pad015[103];
+       u32 pad015[55];
        u32 cm_dsp_clkstctrl;
        u32 pad016[7];
        u32 cm_dsp_dsp_clkctrl;
@@ -515,6 +517,8 @@ struct omap4_prcm_regs {
 #define CM_CLKSEL_DPLL_M_MASK                  (0x7FF << 8)
 #define CM_CLKSEL_DPLL_N_SHIFT                 0
 #define CM_CLKSEL_DPLL_N_MASK                  0x7F
+#define CM_CLKSEL_DCC_EN_SHIFT                 22
+#define CM_CLKSEL_DCC_EN_MASK                  (1 << 22)
 
 #define OMAP4_DPLL_MAX_N       127
 
@@ -596,6 +600,12 @@ struct omap4_prcm_regs {
 /* CM_L3INIT_USBPHY_CLKCTRL */
 #define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK  8
 
+/* CM_MPU_MPU_CLKCTRL */
+#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
+#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK  (1 << 24)
+#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT  25
+#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK   (1 << 25)
+
 /* Clock frequencies */
 #define OMAP_SYS_CLK_FREQ_38_4_MHZ     38400000
 #define OMAP_SYS_CLK_IND_38_4_MHZ      6
@@ -618,6 +628,7 @@ struct omap4_prcm_regs {
 #define PRM_VC_VAL_BYPASS_DATA_SHIFT           16
 #define PRM_VC_VAL_BYPASS_DATA_MASK            0xFF
 
+/* SMPS */
 #define SMPS_I2C_SLAVE_ADDR    0x12
 #define SMPS_REG_ADDR_VCORE1   0x55
 #define SMPS_REG_ADDR_VCORE2   0x5B
@@ -626,6 +637,21 @@ struct omap4_prcm_regs {
 #define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV             607700
 #define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000
 
+/* TPS */
+#define TPS62361_I2C_SLAVE_ADDR                0x60
+#define TPS62361_REG_ADDR_SET0         0x0
+#define TPS62361_REG_ADDR_SET1         0x1
+#define TPS62361_REG_ADDR_SET2         0x2
+#define TPS62361_REG_ADDR_SET3         0x3
+#define TPS62361_REG_ADDR_CTRL         0x4
+#define TPS62361_REG_ADDR_TEMP         0x5
+#define TPS62361_REG_ADDR_RMP_CTRL     0x6
+#define TPS62361_REG_ADDR_CHIP_ID      0x8
+#define TPS62361_REG_ADDR_CHIP_ID_2    0x9
+
+#define TPS62361_BASE_VOLT_MV  500
+#define TPS62361_VSEL0_GPIO    7
+
 /* Defines for DPLL setup */
 #define DPLL_LOCKED_FREQ_TOLERANCE_0           0
 #define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ     500
@@ -653,12 +679,12 @@ struct dpll_regs {
 struct dpll_params {
        u32 m;
        u32 n;
-       u8 m2;
-       u8 m3;
-       u8 m4;
-       u8 m5;
-       u8 m6;
-       u8 m7;
+       s8 m2;
+       s8 m3;
+       s8 m4;
+       s8 m5;
+       s8 m6;
+       s8 m7;
 };
 
 #endif /* _CLOCKS_OMAP4_H_ */