#define OMAP_HSMMC2_BASE 0x480B4100
#define OMAP_HSMMC3_BASE 0x480AD100
-typedef struct hsmmc {
+struct hsmmc {
unsigned char res1[0x10];
unsigned int sysconfig; /* 0x10 */
unsigned int sysstatus; /* 0x14 */
unsigned int ie; /* 0x134 */
unsigned char res4[0x8];
unsigned int capa; /* 0x140 */
-} hsmmc_t;
+};
/*
* OMAP HS MMC Bit definitions
#define NBLK_STPCNT (0x0 << 16)
#define DE_DISABLE (0x0 << 0)
#define BCE_DISABLE (0x0 << 1)
+#define BCE_ENABLE (0x1 << 1)
#define ACEN_DISABLE (0x0 << 2)
#define DDIR_OFFSET (4)
#define DDIR_MASK (0x1 << 4)
#define DDIR_WRITE (0x0 << 4)
#define DDIR_READ (0x1 << 4)
#define MSBS_SGLEBLK (0x0 << 5)
+#define MSBS_MULTIBLK (0x1 << 5)
#define RSP_TYPE_OFFSET (16)
#define RSP_TYPE_MASK (0x3 << 16)
#define RSP_TYPE_NORSP (0x0 << 16)
#define INDEX_MASK (0x3f << 24)
#define INDEX(i) (i << 24)
#define DATI_MASK (0x1 << 1)
-#define DATI_CMDDIS (0x1 << 1)
+#define CMDI_MASK (0x1 << 0)
#define DTW_1_BITMODE (0x0 << 1)
#define DTW_4_BITMODE (0x1 << 1)
+#define DTW_8_BITMODE (0x1 << 5) /* CON[DW8]*/
#define SDBP_PWROFF (0x0 << 8)
#define SDBP_PWRON (0x1 << 8)
#define SDVS_1V8 (0x5 << 9)
#define CLK_400KHZ 1
#define CLK_MISC 2
-typedef struct {
- unsigned int card_type;
- unsigned int version;
- unsigned int mode;
- unsigned int size;
- unsigned int RCA;
-} mmc_card_data;
+#define RSP_TYPE_NONE (RSP_TYPE_NORSP | CCCE_NOCHECK | CICE_NOCHECK)
+#define MMC_CMD0 (INDEX(0) | RSP_TYPE_NONE | DP_NO_DATA | DDIR_WRITE)
+
+/* Clock Configurations and Macros */
+#define MMC_CLOCK_REFERENCE 96 /* MHz */
#define mmc_reg_out(addr, mask, val)\
writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
+int omap_mmc_init(int dev_index, uint host_caps_mask, uint f_max);
+
#endif /* MMC_HOST_DEF_H */