TI: Rework SRAM definitions and maximums

[u-boot] / arch / arm / include / asm / arch-omap4 / omap.h

diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h
index 5f321fe6f0095a3a7ba4901391c6108567b2e29a..b86a7768401cd39e4633fb3bb046da965356a29e 100644 (file)
--- a/arch/arm/include/asm/arch-omap4/omap.h
+++ b/arch/arm/include/asm/arch-omap4/omap.h
@@ -9,23 +9,7 @@
  *     Richard Woodruff <r-woodruff2@ti.com>
  *     Syed Mohammed Khasim <x0khasim@ti.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef _OMAP4_H_
@@ -35,6 +19,8 @@
 #include <asm/types.h>
 #endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
 
+#include <linux/sizes.h>
+
 /*
  * L4 Peripherals - L4 Wakeup and L4 Core now
  */
@@ -47,14 +33,6 @@
 #define DRAM_ADDR_SPACE_START  OMAP44XX_DRAM_ADDR_SPACE_START
 #define DRAM_ADDR_SPACE_END    OMAP44XX_DRAM_ADDR_SPACE_END
 
-/* CONTROL */
-#define CTRL_BASE              (OMAP44XX_L4_CORE_BASE + 0x2000)
-#define CONTROL_PADCONF_CORE   (OMAP44XX_L4_CORE_BASE + 0x100000)
-#define CONTROL_PADCONF_WKUP   (OMAP44XX_L4_CORE_BASE + 0x31E000)
-
-/* LPDDR2 IO regs */
-#define LPDDR2_IO_REGS_BASE    0x4A100638
-
 /* CONTROL_ID_CODE */
 #define CONTROL_ID_CODE                0x4A002204
 
@@ -65,6 +43,7 @@
 #define OMAP4_CONTROL_ID_CODE_ES2_3    0x6B95C02F
 #define OMAP4460_CONTROL_ID_CODE_ES1_0 0x0B94E02F
 #define OMAP4460_CONTROL_ID_CODE_ES1_1 0x2B94E02F
+#define OMAP4470_CONTROL_ID_CODE_ES1_0 0x0B97502F
 
 /* UART */
 #define UART1_BASE             (OMAP44XX_L4_PER_BASE + 0x6a000)
@@ -79,15 +58,6 @@
 /* Watchdog Timer2 - MPU watchdog */
 #define WDT2_BASE              (OMAP44XX_L4_WKUP_BASE + 0x14000)
 
-/* 32KTIMER */
-#define SYNC_32KTIMER_BASE     (OMAP44XX_L4_WKUP_BASE + 0x4000)
-
-/* GPMC */
-#define OMAP44XX_GPMC_BASE     0x50000000
-
-/* SYSTEM CONTROL MODULE */
-#define SYSCTRL_GENERAL_CORE_BASE      0x4A002000
-
 /*
  * Hardware Register Details
  */
@@ -141,43 +111,35 @@ struct s32ktimer {
  */
 #define NON_SECURE_SRAM_START  0x40304000
 #define NON_SECURE_SRAM_END    0x4030E000      /* Not inclusive */
+#define NON_SECURE_SRAM_IMG_END        0x4030C000
+#define SRAM_SCRATCH_SPACE_ADDR        (NON_SECURE_SRAM_IMG_END - SZ_1K)
 /* base address for indirect vectors (internal boot mode) */
 #define SRAM_ROM_VECT_BASE     0x4030D000
-/* Temporary SRAM stack used while low level init is done */
-#define SRAM_SCRATCH_SPACE_ADDR                NON_SECURE_SRAM_START
-/* SRAM scratch space entries */
-#define OMAP4_SRAM_SCRATCH_OMAP4_REV   SRAM_SCRATCH_SPACE_ADDR
-#define OMAP4_SRAM_SCRATCH_EMIF_SIZE   (SRAM_SCRATCH_SPACE_ADDR + 0x4)
-#define OMAP4_SRAM_SCRATCH_EMIF_T_NUM  (SRAM_SCRATCH_SPACE_ADDR + 0xC)
-#define OMAP4_SRAM_SCRATCH_EMIF_T_DEN  (SRAM_SCRATCH_SPACE_ADDR + 0x10)
-#define OMAP_SRAM_SCRATCH_PRCM_PTR      (SRAM_SCRATCH_SPACE_ADDR + 0x14)
-#define OMAP_SRAM_SCRATCH_DPLLS_PTR     (SRAM_SCRATCH_SPACE_ADDR + 0x18)
-#define OMAP_SRAM_SCRATCH_VCORES_PTR   (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
-#define OMAP4_SRAM_SCRATCH_SYS_CTRL    (SRAM_SCRATCH_SPACE_ADDR + 0x20)
-#define OMAP4_SRAM_SCRATCH_SPACE_END   (SRAM_SCRATCH_SPACE_ADDR + 0x24)
-
-/* ROM code defines */
-/* Boot device */
-#define BOOT_DEVICE_MASK       0xFF
-#define BOOT_DEVICE_OFFSET     0x8
-#define DEV_DESC_PTR_OFFSET    0x4
-#define DEV_DATA_PTR_OFFSET    0x18
-#define BOOT_MODE_OFFSET       0x8
-#define RESET_REASON_OFFSET    0x9
-#define CH_FLAGS_OFFSET                0xA
-
-#define CH_FLAGS_CHSETTINGS    (0x1 << 0)
-#define CH_FLAGS_CHRAM         (0x1 << 1)
-#define CH_FLAGS_CHFLASH       (0x1 << 2)
-#define CH_FLAGS_CHMMCSD       (0x1 << 3)
 
+/* ABB settings */
+#define OMAP_ABB_SETTLING_TIME         50
+#define OMAP_ABB_CLOCK_CYCLES          16
+
+/* ABB tranxdone mask */
+#define OMAP_ABB_MPU_TXDONE_MASK       (0x1 << 7)
+
+#define OMAP44XX_SAR_RAM_BASE          0x4a326000
+#define OMAP_REBOOT_REASON_OFFSET      0xA0C
+#define OMAP_REBOOT_REASON_SIZE                0x0F
+
+/* Boot parameters */
 #ifndef __ASSEMBLY__
 struct omap_boot_parameters {
-       char *boot_message;
-       unsigned int mem_boot_descriptor;
-       unsigned char omap_bootdevice;
+       unsigned int boot_message;
+       unsigned int boot_device_descriptor;
+       unsigned char boot_device;
        unsigned char reset_reason;
        unsigned char ch_flags;
 };
+
+int omap_reboot_mode(char *mode, unsigned int length);
+int omap_reboot_mode_clear(void);
+int omap_reboot_mode_store(char *mode);
 #endif
+
 #endif