/* CONTROL_ID_CODE */
#define CONTROL_ID_CODE 0x4A002204
+#define STD_FUSE_DIE_ID_0 0x4A002200
+#define STD_FUSE_DIE_ID_1 0x4A002208
+#define STD_FUSE_DIE_ID_2 0x4A00220c
+#define STD_FUSE_DIE_ID_3 0x4A002210
#define OMAP4_CONTROL_ID_CODE_ES1_0 0x0B85202F
#define OMAP4_CONTROL_ID_CODE_ES2_0 0x1B85202F
/* Watchdog Timer2 - MPU watchdog */
#define WDT2_BASE (OMAP44XX_L4_WKUP_BASE + 0x14000)
-/* GPMC */
-#define OMAP44XX_GPMC_BASE 0x50000000
-
/*
* Hardware Register Details
*/
*/
#define NON_SECURE_SRAM_START 0x40304000
#define NON_SECURE_SRAM_END 0x4030E000 /* Not inclusive */
-#define SRAM_SCRATCH_SPACE_ADDR NON_SECURE_SRAM_START
+#define SRAM_SCRATCH_SPACE_ADDR 0x4030C000
/* base address for indirect vectors (internal boot mode) */
#define SRAM_ROM_VECT_BASE 0x4030D000