/* CONTROL */
#define CTRL_BASE (OMAP44XX_L4_CORE_BASE + 0x2000)
+#define CONTROL_PADCONF_CORE (OMAP44XX_L4_CORE_BASE + 0x100000)
+#define CONTROL_PADCONF_WKUP (OMAP44XX_L4_CORE_BASE + 0x31E000)
/* UART */
#define UART1_BASE (OMAP44XX_L4_PER_BASE + 0x6a000)
#define SYNC_32KTIMER_BASE (OMAP44XX_L4_WKUP_BASE + 0x4000)
/* GPMC */
-#define GPMC_BASE 0x50000000
+#define OMAP44XX_GPMC_BASE 0x50000000
/*
* Hardware Register Details