omap: add basic SPL support

[u-boot] / arch / arm / include / asm / arch-omap4 / omap4.h

diff --git a/arch/arm/include/asm/arch-omap4/omap4.h b/arch/arm/include/asm/arch-omap4/omap4.h
index a30bb332e8be83988d7fd0c8978e970f54f355e7..a8dbedb45d489dc666bc605b62f41ef80ec77da8 100644 (file)
--- a/arch/arm/include/asm/arch-omap4/omap4.h
+++ b/arch/arm/include/asm/arch-omap4/omap4.h
@@ -51,6 +51,20 @@
 #define CONTROL_PADCONF_CORE   (OMAP44XX_L4_CORE_BASE + 0x100000)
 #define CONTROL_PADCONF_WKUP   (OMAP44XX_L4_CORE_BASE + 0x31E000)
 
+/* LPDDR2 IO regs */
+#define LPDDR2_IO_REGS_BASE    0x4A100638
+
+#define CONTROL_EFUSE_2                0x4A100704
+
+/* CONTROL_ID_CODE */
+#define CONTROL_ID_CODE                0x4A002204
+
+#define OMAP4_CONTROL_ID_CODE_ES1_0    0x0B85202F
+#define OMAP4_CONTROL_ID_CODE_ES2_0    0x1B85202F
+#define OMAP4_CONTROL_ID_CODE_ES2_1    0x3B95C02F
+#define OMAP4_CONTROL_ID_CODE_ES2_2    0x4B95C02F
+#define OMAP4_CONTROL_ID_CODE_ES2_3    0x6B95C02F
+
 /* UART */
 #define UART1_BASE             (OMAP44XX_L4_PER_BASE + 0x6a000)
 #define UART2_BASE             (OMAP44XX_L4_PER_BASE + 0x6c000)
@@ -70,12 +84,6 @@
 /* GPMC */
 #define OMAP44XX_GPMC_BASE     0x50000000
 
-/* DMM */
-#define OMAP44XX_DMM_BASE              0x4E000000
-#define DMM_LISA_MAP_BASE              (OMAP44XX_DMM_BASE + 0x40)
-#define DMM_LISA_MAP_SYS_SIZE_MASK     (7 << 20)
-#define DMM_LISA_MAP_SYS_SIZE_SHIFT    20
-#define DMM_LISA_MAP_SYS_ADDR_MASK     (0xFF << 24)
 /*
  * Hardware Register Details
  */
@@ -119,13 +127,21 @@ struct s32ktimer {
 /* base address for indirect vectors (internal boot mode) */
 #define SRAM_ROM_VECT_BASE     0x4030D000
 /* Temporary SRAM stack used while low level init is done */
-#define LOW_LEVEL_SRAM_STACK   NON_SECURE_SRAM_END
-
-/*
- * OMAP4 real hardware:
- * TODO: Change this to the IDCODE in the hw regsiter
- */
-#define CPU_OMAP4430_ES10      1
-#define CPU_OMAP4430_ES20      2
+#define LOW_LEVEL_SRAM_STACK           NON_SECURE_SRAM_END
+#define SRAM_SCRATCH_SPACE_ADDR                NON_SECURE_SRAM_START
+/* SRAM scratch space entries */
+#define OMAP4_SRAM_SCRATCH_OMAP4_REV   SRAM_SCRATCH_SPACE_ADDR
+#define OMAP4_SRAM_SCRATCH_EMIF_SIZE   (SRAM_SCRATCH_SPACE_ADDR + 0x4)
+#define OMAP4_SRAM_SCRATCH_EMIF_T_NUM  (SRAM_SCRATCH_SPACE_ADDR + 0xC)
+#define OMAP4_SRAM_SCRATCH_EMIF_T_DEN  (SRAM_SCRATCH_SPACE_ADDR + 0x10)
+#define OMAP4_SRAM_SCRATCH_SPACE_END   (SRAM_SCRATCH_SPACE_ADDR + 0x14)
+
+/* Silicon revisions */
+#define OMAP4430_SILICON_ID_INVALID    0xFFFFFFFF
+#define OMAP4430_ES1_0 0x44300100
+#define OMAP4430_ES2_0 0x44300200
+#define OMAP4430_ES2_1 0x44300210
+#define OMAP4430_ES2_2 0x44300220
+#define OMAP4430_ES2_3 0x44300230
 
 #endif