Merge git://git.denx.de/u-boot-mpc85xx

[u-boot] / arch / arm / include / asm / arch-omap5 / clock.h

diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index 5cbbc44b0ac3ec78a4fd72b1c80772fdea5c6de5..0c99bbdc9320326e843099d0d399f305ca903ced 100644 (file)
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -137,6 +137,9 @@
 #define HSMMC_CLKCTRL_CLKSEL_MASK              (1 << 24)
 #define HSMMC_CLKCTRL_CLKSEL_DIV_MASK          (1 << 25)
 
+/* CM_L3INIT_SATA_CLKCTRL */
+#define SATA_CLKCTRL_OPTFCLKEN_MASK            (1 << 8)
+
 /* CM_WKUP_GPTIMER1_CLKCTRL */
 #define GPTIMER1_CLKCTRL_CLKSEL_MASK           (1 << 24)
 
@@ -169,6 +172,9 @@
 /* CM_COREAON_USB_PHY_CORE_CLKCTRL */
 #define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K   (1 << 8)
 
+/* CM_COREAON_L3INIT_60M_GFCLK_CLKCTRL */
+#define L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK     (1 << 8)
+
 /* CM_L3INIT_USB_OTG_SS_CLKCTRL */
 #define OTG_SS_CLKCTRL_MODULEMODE_HW   (1 << 0)
 #define OPTFCLKEN_REFCLK960M                   (1 << 8)
@@ -202,6 +208,10 @@
 /* PRM_VC_VAL_BYPASS */
 #define PRM_VC_I2C_CHANNEL_FREQ_KHZ    400
 
+/* CTRL_CORE_SRCOMP_NORTH_SIDE */
+#define USB2PHY_DISCHGDET      (1 << 29)
+#define USB2PHY_AUTORESUME_EN (1 << 30)
+
 /* SMPS */
 #define SMPS_I2C_SLAVE_ADDR    0x12
 #define SMPS_REG_ADDR_12_MPU   0x23
@@ -229,12 +239,22 @@
 #define VDD_MPU_ES2_LOW 880
 #define VDD_MM_ES2_LOW 880
 
-/* TPS659038 Voltage settings in mv for OPP_NOMINAL */
-#define VDD_MPU_DRA752         1090
-#define VDD_EVE_DRA752         1060
-#define VDD_GPU_DRA752         1060
-#define VDD_CORE_DRA752                1030
-#define VDD_IVA_DRA752         1060
+/* DRA74x/75x/72x voltage settings in mv for OPP_NOM per DM */
+#define VDD_MPU_DRA7_NOM       1150
+#define VDD_CORE_DRA7_NOM      1150
+#define VDD_EVE_DRA7_NOM       1060
+#define VDD_GPU_DRA7_NOM       1060
+#define VDD_IVA_DRA7_NOM       1060
+
+/* DRA74x/75x/72x voltage settings in mv for OPP_OD per DM */
+#define VDD_EVE_DRA7_OD                1150
+#define VDD_GPU_DRA7_OD                1150
+#define VDD_IVA_DRA7_OD                1150
+
+/* DRA74x/75x/72x voltage settings in mv for OPP_HIGH per DM */
+#define VDD_EVE_DRA7_HIGH      1250
+#define VDD_GPU_DRA7_HIGH      1250
+#define VDD_IVA_DRA7_HIGH      1250
 
 /* Efuse register offsets for DRA7xx platform */
 #define DRA752_EFUSE_BASE      0x4A002000
@@ -266,16 +286,66 @@
 /* STD_FUSE_OPP_VMIN_MPU_4 */
 #define STD_FUSE_OPP_VMIN_MPU_HIGH     (DRA752_EFUSE_BASE + 0x1B28)
 
+#if defined(CONFIG_DRA7_MPU_OPP_HIGH)
+#define DRA7_MPU_OPP   OPP_HIGH
+#elif defined(CONFIG_DRA7_MPU_OPP_OD)
+#define DRA7_MPU_OPP   OPP_OD
+#else /* OPP_NOM default */
+#define DRA7_MPU_OPP   OPP_NOM
+#endif
+
+/* OPP_NOM only available option for CORE */
+#define DRA7_CORE_OPP  OPP_NOM
+
+#if defined(CONFIG_DRA7_DSPEVE_OPP_HIGH)
+#define DRA7_DSPEVE_OPP        OPP_HIGH
+#elif defined(CONFIG_DRA7_DSPEVE_OPP_OD)
+#define DRA7_DSPEVE_OPP        OPP_OD
+#else /* OPP_NOM default */
+#define DRA7_DSPEVE_OPP        OPP_NOM
+#endif
+
+#if defined(CONFIG_DRA7_IVA_OPP_HIGH)
+#define DRA7_IVA_OPP   OPP_HIGH
+#elif defined(CONFIG_DRA7_IVA_OPP_OD)
+#define DRA7_IVA_OPP   OPP_OD
+#else /* OPP_NOM default */
+#define DRA7_IVA_OPP   OPP_NOM
+#endif
+
+#if defined(CONFIG_DRA7_GPU_OPP_HIGH)
+#define DRA7_GPU_OPP   OPP_HIGH
+#elif defined(CONFIG_DRA7_GPU_OPP_OD)
+#define DRA7_GPU_OPP   OPP_OD
+#else /* OPP_NOM default */
+#define DRA7_GPU_OPP   OPP_NOM
+#endif
+
 /* Standard offset is 0.5v expressed in uv */
 #define PALMAS_SMPS_BASE_VOLT_UV 500000
 
+/* Offset is 0.73V for LP873x */
+#define LP873X_BUCK_BASE_VOLT_UV               730000
+
 /* TPS659038 */
 #define TPS659038_I2C_SLAVE_ADDR               0x58
-#define TPS659038_REG_ADDR_SMPS12_MPU          0x23
-#define TPS659038_REG_ADDR_SMPS45_EVE          0x2B
-#define TPS659038_REG_ADDR_SMPS6_GPU           0x2F
-#define TPS659038_REG_ADDR_SMPS7_CORE          0x33
-#define TPS659038_REG_ADDR_SMPS8_IVA           0x37
+#define TPS659038_REG_ADDR_SMPS12              0x23
+#define TPS659038_REG_ADDR_SMPS45              0x2B
+#define TPS659038_REG_ADDR_SMPS6               0x2F
+#define TPS659038_REG_ADDR_SMPS7               0x33
+#define TPS659038_REG_ADDR_SMPS8               0x37
+
+/* TPS65917 */
+#define TPS65917_I2C_SLAVE_ADDR                0x58
+#define TPS65917_REG_ADDR_SMPS1                0x23
+#define TPS65917_REG_ADDR_SMPS2                0x27
+#define TPS65917_REG_ADDR_SMPS3                0x2F
+
+/* LP873X */
+#define LP873X_I2C_SLAVE_ADDR          0x60
+#define LP873X_REG_ADDR_BUCK0          0x6
+#define LP873X_REG_ADDR_BUCK1          0x7
+#define LP873X_REG_ADDR_LDO1           0xA
 
 /* TPS */
 #define TPS62361_I2C_SLAVE_ADDR                0x60
@@ -300,14 +370,7 @@
 #define DPLL_NO_LOCK   0
 #define DPLL_LOCK      1
 
-/*
- * MAX value for PRM_RSTTIME[9:0]RSTTIME1 stored is 0x3ff.
- * 0x3ff is in the no of FUNC_32K_CLK cycles. Converting cycles
- * into microsec and passing the value.
- */
-#define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC        31219
-
-#ifdef CONFIG_DRA7XX
+#if defined(CONFIG_DRA7XX)
 #define V_OSCK                 20000000        /* Clock output from T2 */
 #else
 #define V_OSCK                 19200000        /* Clock output from T2 */
@@ -315,6 +378,9 @@
 
 #define V_SCLK V_OSCK
 
+/* CKO buffer control */
+#define CKOBUFFER_CLK_ENABLE_MASK      (1 << 28)
+
 /* AUXCLKx reg fields */
 #define AUXCLK_ENABLE_MASK             (1 << 8)
 #define AUXCLK_SRCSELECT_SHIFT         1