Merge git://git.denx.de/u-boot-mpc85xx

[u-boot] / arch / arm / include / asm / arch-omap5 / clock.h

diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index f6ea1df1a450867fae7a50d0145d8801030e3926..0c99bbdc9320326e843099d0d399f305ca903ced 100644 (file)
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -286,23 +286,47 @@
 /* STD_FUSE_OPP_VMIN_MPU_4 */
 #define STD_FUSE_OPP_VMIN_MPU_HIGH     (DRA752_EFUSE_BASE + 0x1B28)
 
-/* Common voltage and Efuse register macros */
-/* DRA74x/DRA75x/DRA72x */
-#define VDD_MPU_DRA7                   VDD_MPU_DRA7_NOM
-#define VDD_CORE_DRA7                  VDD_CORE_DRA7_NOM
-#define VDD_EVE_DRA7                   VDD_EVE_DRA7_NOM
-#define VDD_GPU_DRA7                   VDD_GPU_DRA7_NOM
-#define VDD_IVA_DRA7                   VDD_IVA_DRA7_NOM
-
-#define STD_FUSE_OPP_VMIN_MPU          STD_FUSE_OPP_VMIN_MPU_NOM
-#define STD_FUSE_OPP_VMIN_CORE         STD_FUSE_OPP_VMIN_CORE_NOM
-#define STD_FUSE_OPP_VMIN_DSPEVE       STD_FUSE_OPP_VMIN_DSPEVE_NOM
-#define STD_FUSE_OPP_VMIN_GPU          STD_FUSE_OPP_VMIN_GPU_NOM
-#define STD_FUSE_OPP_VMIN_IVA          STD_FUSE_OPP_VMIN_IVA_NOM
+#if defined(CONFIG_DRA7_MPU_OPP_HIGH)
+#define DRA7_MPU_OPP   OPP_HIGH
+#elif defined(CONFIG_DRA7_MPU_OPP_OD)
+#define DRA7_MPU_OPP   OPP_OD
+#else /* OPP_NOM default */
+#define DRA7_MPU_OPP   OPP_NOM
+#endif
+
+/* OPP_NOM only available option for CORE */
+#define DRA7_CORE_OPP  OPP_NOM
+
+#if defined(CONFIG_DRA7_DSPEVE_OPP_HIGH)
+#define DRA7_DSPEVE_OPP        OPP_HIGH
+#elif defined(CONFIG_DRA7_DSPEVE_OPP_OD)
+#define DRA7_DSPEVE_OPP        OPP_OD
+#else /* OPP_NOM default */
+#define DRA7_DSPEVE_OPP        OPP_NOM
+#endif
+
+#if defined(CONFIG_DRA7_IVA_OPP_HIGH)
+#define DRA7_IVA_OPP   OPP_HIGH
+#elif defined(CONFIG_DRA7_IVA_OPP_OD)
+#define DRA7_IVA_OPP   OPP_OD
+#else /* OPP_NOM default */
+#define DRA7_IVA_OPP   OPP_NOM
+#endif
+
+#if defined(CONFIG_DRA7_GPU_OPP_HIGH)
+#define DRA7_GPU_OPP   OPP_HIGH
+#elif defined(CONFIG_DRA7_GPU_OPP_OD)
+#define DRA7_GPU_OPP   OPP_OD
+#else /* OPP_NOM default */
+#define DRA7_GPU_OPP   OPP_NOM
+#endif
 
 /* Standard offset is 0.5v expressed in uv */
 #define PALMAS_SMPS_BASE_VOLT_UV 500000
 
+/* Offset is 0.73V for LP873x */
+#define LP873X_BUCK_BASE_VOLT_UV               730000
+
 /* TPS659038 */
 #define TPS659038_I2C_SLAVE_ADDR               0x58
 #define TPS659038_REG_ADDR_SMPS12              0x23
@@ -317,6 +341,11 @@
 #define TPS65917_REG_ADDR_SMPS2                0x27
 #define TPS65917_REG_ADDR_SMPS3                0x2F
 
+/* LP873X */
+#define LP873X_I2C_SLAVE_ADDR          0x60
+#define LP873X_REG_ADDR_BUCK0          0x6
+#define LP873X_REG_ADDR_BUCK1          0x7
+#define LP873X_REG_ADDR_LDO1           0xA
 
 /* TPS */
 #define TPS62361_I2C_SLAVE_ADDR                0x60
@@ -341,13 +370,6 @@
 #define DPLL_NO_LOCK   0
 #define DPLL_LOCK      1
 
-/*
- * MAX value for PRM_RSTTIME[9:0]RSTTIME1 stored is 0x3ff.
- * 0x3ff is in the no of FUNC_32K_CLK cycles. Converting cycles
- * into microsec and passing the value.
- */
-#define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC        31219
-
 #if defined(CONFIG_DRA7XX)
 #define V_OSCK                 20000000        /* Clock output from T2 */
 #else