/* TPS659038 */
#define TPS659038_I2C_SLAVE_ADDR 0x58
-#define TPS659038_REG_ADDR_SMPS12_MPU 0x23
-#define TPS659038_REG_ADDR_SMPS45_EVE 0x2B
-#define TPS659038_REG_ADDR_SMPS6_GPU 0x2F
-#define TPS659038_REG_ADDR_SMPS7_CORE 0x33
-#define TPS659038_REG_ADDR_SMPS8_IVA 0x37
+#define TPS659038_REG_ADDR_SMPS12 0x23
+#define TPS659038_REG_ADDR_SMPS45 0x2B
+#define TPS659038_REG_ADDR_SMPS6 0x2F
+#define TPS659038_REG_ADDR_SMPS7 0x33
+#define TPS659038_REG_ADDR_SMPS8 0x37
/* TPS */
#define TPS62361_I2C_SLAVE_ADDR 0x60
*/
#define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC 31219
-#ifdef CONFIG_DRA7XX
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
#define V_OSCK 20000000 /* Clock output from T2 */
#else
#define V_OSCK 19200000 /* Clock output from T2 */
#define V_SCLK V_OSCK
+/* CKO buffer control */
+#define CKOBUFFER_CLK_ENABLE_MASK (1 << 28)
+
/* AUXCLKx reg fields */
#define AUXCLK_ENABLE_MASK (1 << 8)
#define AUXCLK_SRCSELECT_SHIFT 1