ARM: DRA7: Add macros for voltage values for all OPPs

[u-boot] / arch / arm / include / asm / arch-omap5 / clock.h

diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index 7eacba2686286539b0405192b9502e88fa888a09..551c9277f2a74fa3a0c8e050a4987d690f6b1fb6 100644 (file)
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -172,6 +172,9 @@
 /* CM_COREAON_USB_PHY_CORE_CLKCTRL */
 #define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K   (1 << 8)
 
+/* CM_COREAON_L3INIT_60M_GFCLK_CLKCTRL */
+#define L3INIT_CLKCTRL_OPTFCLKEN_60M_GFCLK     (1 << 8)
+
 /* CM_L3INIT_USB_OTG_SS_CLKCTRL */
 #define OTG_SS_CLKCTRL_MODULEMODE_HW   (1 << 0)
 #define OPTFCLKEN_REFCLK960M                   (1 << 8)
@@ -236,12 +239,22 @@
 #define VDD_MPU_ES2_LOW 880
 #define VDD_MM_ES2_LOW 880
 
-/* TPS659038 Voltage settings in mv for OPP_NOMINAL */
-#define VDD_MPU_DRA752         1090
-#define VDD_EVE_DRA752         1060
-#define VDD_GPU_DRA752         1060
-#define VDD_CORE_DRA752                1030
-#define VDD_IVA_DRA752         1060
+/* DRA74x/75x/72x voltage settings in mv for OPP_NOM per DM */
+#define VDD_MPU_DRA7_NOM       1150
+#define VDD_CORE_DRA7_NOM      1150
+#define VDD_EVE_DRA7_NOM       1060
+#define VDD_GPU_DRA7_NOM       1060
+#define VDD_IVA_DRA7_NOM       1060
+
+/* DRA74x/75x/72x voltage settings in mv for OPP_OD per DM */
+#define VDD_EVE_DRA7_OD                1150
+#define VDD_GPU_DRA7_OD                1150
+#define VDD_IVA_DRA7_OD                1150
+
+/* DRA74x/75x/72x voltage settings in mv for OPP_HIGH per DM */
+#define VDD_EVE_DRA7_HIGH      1250
+#define VDD_GPU_DRA7_HIGH      1250
+#define VDD_IVA_DRA7_HIGH      1250
 
 /* Efuse register offsets for DRA7xx platform */
 #define DRA752_EFUSE_BASE      0x4A002000
@@ -273,6 +286,20 @@
 /* STD_FUSE_OPP_VMIN_MPU_4 */
 #define STD_FUSE_OPP_VMIN_MPU_HIGH     (DRA752_EFUSE_BASE + 0x1B28)
 
+/* Common voltage and Efuse register macros */
+/* DRA74x/DRA75x/DRA72x */
+#define VDD_MPU_DRA7                   VDD_MPU_DRA7_NOM
+#define VDD_CORE_DRA7                  VDD_CORE_DRA7_NOM
+#define VDD_EVE_DRA7                   VDD_EVE_DRA7_NOM
+#define VDD_GPU_DRA7                   VDD_GPU_DRA7_NOM
+#define VDD_IVA_DRA7                   VDD_IVA_DRA7_NOM
+
+#define STD_FUSE_OPP_VMIN_MPU          STD_FUSE_OPP_VMIN_MPU_NOM
+#define STD_FUSE_OPP_VMIN_CORE         STD_FUSE_OPP_VMIN_CORE_NOM
+#define STD_FUSE_OPP_VMIN_DSPEVE       STD_FUSE_OPP_VMIN_DSPEVE_NOM
+#define STD_FUSE_OPP_VMIN_GPU          STD_FUSE_OPP_VMIN_GPU_NOM
+#define STD_FUSE_OPP_VMIN_IVA          STD_FUSE_OPP_VMIN_IVA_NOM
+
 /* Standard offset is 0.5v expressed in uv */
 #define PALMAS_SMPS_BASE_VOLT_UV 500000
 
@@ -284,6 +311,13 @@
 #define TPS659038_REG_ADDR_SMPS7               0x33
 #define TPS659038_REG_ADDR_SMPS8               0x37
 
+/* TPS65917 */
+#define TPS65917_I2C_SLAVE_ADDR                0x58
+#define TPS65917_REG_ADDR_SMPS1                0x23
+#define TPS65917_REG_ADDR_SMPS2                0x27
+#define TPS65917_REG_ADDR_SMPS3                0x2F
+
+
 /* TPS */
 #define TPS62361_I2C_SLAVE_ADDR                0x60
 #define TPS62361_REG_ADDR_SET0         0x0
@@ -314,7 +348,7 @@
  */
 #define CONFIG_DEFAULT_OMAP_RESET_TIME_MAX_USEC        31219
 
-#ifdef CONFIG_DRA7XX
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
 #define V_OSCK                 20000000        /* Clock output from T2 */
 #else
 #define V_OSCK                 19200000        /* Clock output from T2 */