Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'

[u-boot] / arch / arm / include / asm / arch-omap5 / clocks.h

diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h
index 67e74ca4024593dd3630aa05a62a07da1cb224c0..cfde3743330368c0368917bdd24973010255fb9e 100644 (file)
--- a/arch/arm/include/asm/arch-omap5/clocks.h
+++ b/arch/arm/include/asm/arch-omap5/clocks.h
@@ -176,9 +176,9 @@
 
 /* CM_MPU_MPU_CLKCTRL */
 #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
-#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK  (1 << 24)
-#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT  25
-#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK   (1 << 25)
+#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK  (3 << 24)
+#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT  26
+#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK   (1 << 26)
 
 /* CM_WKUPAON_SCRM_CLKCTRL */
 #define OPTFCLKEN_SCRM_PER_SHIFT               9
@@ -186,6 +186,10 @@
 #define OPTFCLKEN_SCRM_CORE_SHIFT              8
 #define OPTFCLKEN_SCRM_CORE_MASK               (1 << 8)
 
+/* CM_COREAON_IO_SRCOMP_CLKCTRL */
+#define OPTFCLKEN_SRCOMP_FCLK_SHIFT            8
+#define OPTFCLKEN_SRCOMP_FCLK_MASK             (1 << 8)
+
 /* Clock frequencies */
 #define OMAP_SYS_CLK_FREQ_38_4_MHZ     38400000
 #define OMAP_SYS_CLK_IND_38_4_MHZ      6
@@ -201,12 +205,25 @@
 #define SMPS_REG_ADDR_8_CORE   0x37
 
 /* PALMAS VOLTAGE SETTINGS in mv for OPP_NOMINAL */
-#define VDD_MPU                1000
-#define VDD_MM         1000
+/* ES1.0 settings */
+#define VDD_MPU                1040
+#define VDD_MM         1040
 #define VDD_CORE       1040
-#define VDD_MPU_5432   1150
-#define VDD_MM_5432    1150
-#define VDD_CORE_5432  1150
+
+#define VDD_MPU_LOW    890
+#define VDD_MM_LOW     890
+#define VDD_CORE_LOW   890
+
+/* ES2.0 settings */
+#define VDD_MPU_ES2    1060
+#define VDD_MM_ES2     1025
+#define VDD_CORE_ES2   1040
+
+#define VDD_MPU_ES2_HIGH 1250
+#define VDD_MM_ES2_OD  1120
+
+#define VDD_MPU_ES2_LOW 880
+#define VDD_MM_ES2_LOW 880
 
 /* Standard offset is 0.5v expressed in uv */
 #define PALMAS_SMPS_BASE_VOLT_UV 500000
@@ -234,58 +251,4 @@
 #define DPLL_NO_LOCK   0
 #define DPLL_LOCK      1
 
-#define NUM_SYS_CLKS   7
-
-struct dpll_regs {
-       u32 cm_clkmode_dpll;
-       u32 cm_idlest_dpll;
-       u32 cm_autoidle_dpll;
-       u32 cm_clksel_dpll;
-       u32 cm_div_m2_dpll;
-       u32 cm_div_m3_dpll;
-       u32 cm_div_h11_dpll;
-       u32 cm_div_h12_dpll;
-       u32 cm_div_h13_dpll;
-       u32 cm_div_h14_dpll;
-       u32 reserved[3];
-       u32 cm_div_h22_dpll;
-       u32 cm_div_h23_dpll;
-};
-
-/* DPLL parameter table */
-struct dpll_params {
-       u32 m;
-       u32 n;
-       s8 m2;
-       s8 m3;
-       s8 h11;
-       s8 h12;
-       s8 h13;
-       s8 h14;
-       s8 h22;
-       s8 h23;
-};
-
-extern const u32 sys_clk_array[8];
-
-void scale_vcores(void);
-void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv);
-u32 get_offset_code(u32 offset);
-u32 omap_ddr_clk(void);
-void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
-void setup_post_dividers(u32 const base, const struct dpll_params *params);
-u32 get_sys_clk_index(void);
-void enable_basic_clocks(void);
-void enable_non_essential_clocks(void);
-void enable_basic_uboot_clocks(void);
-void do_enable_clocks(u32 const *clk_domains,
-                     u32 const *clk_modules_hw_auto,
-                     u32 const *clk_modules_explicit_en,
-                     u8 wait_for_enable);
-const struct dpll_params *get_mpu_dpll_params(void);
-const struct dpll_params *get_core_dpll_params(void);
-const struct dpll_params *get_per_dpll_params(void);
-const struct dpll_params *get_iva_dpll_params(void);
-const struct dpll_params *get_usb_dpll_params(void);
-const struct dpll_params *get_abe_dpll_params(void);
 #endif /* _CLOCKS_OMAP5_H_ */