Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

[u-boot] / arch / arm / include / asm / arch-omap5 / omap.h

diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index ddf5c7a8eae7ddd5c46919429dac377d084ddb6f..2fd5cda6238f431e207372c0857d1b89f679b7c7 100644 (file)
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -33,7 +33,7 @@
 #define CONTROL_ID_CODE                CONTROL_CORE_ID_CODE
 #endif
 
-#ifdef CONFIG_DRA7XX
+#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX)
 #define DRA7_USB_OTG_SS1_BASE          0x48890000
 #define DRA7_USB_OTG_SS1_GLUE_BASE     0x48880000
 #define DRA7_USB3_PHY1_PLL_CTRL                0x4A084C00
@@ -43,6 +43,12 @@
 #define DRA7_USB_OTG_SS2_BASE          0x488D0000
 #define DRA7_USB_OTG_SS2_GLUE_BASE     0x488C0000
 #define DRA7_USB2_PHY2_POWER           0x4A002E74
+#else
+#define OMAP5XX_USB_OTG_SS_BASE                0x4A030000
+#define OMAP5XX_USB_OTG_SS_GLUE_BASE   0x4A020000
+#define OMAP5XX_USB3_PHY_PLL_CTRL      0x4A084C00
+#define OMAP5XX_USB3_PHY_POWER         0x4A002370
+#define OMAP5XX_USB2_PHY_POWER         0x4A002300
 #endif
 
 /* To be verified */
@@ -54,6 +60,7 @@
 #define DRA752_CONTROL_ID_CODE_ES1_1           0x1B99002F
 #define DRA752_CONTROL_ID_CODE_ES2_0           0x2B99002F
 #define DRA722_CONTROL_ID_CODE_ES1_0           0x0B9BC02F
+#define DRA722_CONTROL_ID_CODE_ES2_0           0x1B9BC02F
 
 /* UART */
 #define UART1_BASE             (OMAP54XX_L4_PER_BASE + 0x6a000)
@@ -208,6 +215,10 @@ struct s32ktimer {
 
 /* ABB tranxdone mask */
 #define OMAP_ABB_MPU_TXDONE_MASK               (0x1 << 7)
+#define OMAP_ABB_MM_TXDONE_MASK                        (0x1 << 31)
+#define OMAP_ABB_IVA_TXDONE_MASK               (0x1 << 30)
+#define OMAP_ABB_EVE_TXDONE_MASK               (0x1 << 29)
+#define OMAP_ABB_GPU_TXDONE_MASK               (0x1 << 28)
 
 /* ABB efuse masks */
 #define OMAP5_ABB_FUSE_VSET_MASK               (0x1F << 24)
@@ -235,6 +246,8 @@ struct ctrl_ioregs {
        u32 ctrl_ddr_ctrl_ext_0;
 };
 
+void clrset_spare_register(u8 spare_type, u32 clear_bits, u32 set_bits);
+
 #endif /* __ASSEMBLY__ */
 
 /* Boot parameters */