ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register value

[u-boot] / arch / arm / include / asm / arch-rmobile / r8a7791.h

diff --git a/arch/arm/include/asm/arch-rmobile/r8a7791.h b/arch/arm/include/asm/arch-rmobile/r8a7791.h
index 26a0bd58ff79f5f77728aa6983f59e4f0e202e4e..1d06b651f4852e2f5f82e50a94a0e1654fcf88ba 100644 (file)
--- a/arch/arm/include/asm/arch-rmobile/r8a7791.h
+++ b/arch/arm/include/asm/arch-rmobile/r8a7791.h
@@ -17,6 +17,11 @@
 /* SH-I2C */
 #define CONFIG_SYS_I2C_SH_BASE2        0xE60B0000
 
+/* SDHI */
+#define CONFIG_SYS_SH_SDHI1_BASE 0xEE140000
+#define CONFIG_SYS_SH_SDHI2_BASE 0xEE160000
+#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 3
+
 #define DBSC3_1_QOS_R0_BASE    0xE67A1000
 #define DBSC3_1_QOS_R1_BASE    0xE67A1100
 #define DBSC3_1_QOS_R2_BASE    0xE67A1200
@@ -51,6 +56,19 @@
 #define DBSC3_1_QOS_W15_BASE   0xE67A2F00
 #define DBSC3_1_DBADJ2         0xE67A00C8
 
+/* Module stop control/status register bits */
+#define MSTP0_BITS     0x00640801
+#define MSTP1_BITS     0x9B6C9B5A
+#define MSTP2_BITS     0x100D21FC
+#define MSTP3_BITS     0xF08CD810
+#define MSTP4_BITS     0x800001C4
+#define MSTP5_BITS     0x44C00046
+#define MSTP7_BITS     0x05BFE618
+#define MSTP8_BITS     0x40C0FE85
+#define MSTP9_BITS     0xFF979FFF
+#define MSTP10_BITS    0xFFFEFFE0
+#define MSTP11_BITS    0x000001C0
+
 #define R8A7791_CUT_ES2X       2
 #define IS_R8A7791_ES2()       \
        (rmobile_get_cpu_rev_integer() == R8A7791_CUT_ES2X)