rockchip: rk3368: Add clock driver

[u-boot] / arch / arm / include / asm / arch-rockchip / cru_rk3288.h

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
index 7ebcc405e76c2d4580a161c613d629ca1f7d553d..d575f4a16396012d3fbb3e1faad21018b8d3271e 100644 (file)
--- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
+++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h
@@ -25,6 +25,13 @@
 #define PERI_HCLK_HZ   148500000
 #define PERI_PCLK_HZ   74250000
 
+/* Private data for the clock driver - used by rockchip_get_cru() */
+struct rk3288_clk_priv {
+       struct rk3288_grf *grf;
+       struct rk3288_cru *cru;
+       ulong rate;
+};
+
 struct rk3288_cru {
        struct rk3288_pll {
                u32 con0;
@@ -90,6 +97,23 @@ enum {
        SDIO0_DIV_MASK          = 0x3f,
 };
 
+/* CRU_CLKSEL21_CON */
+enum {
+       MAC_DIV_CON_SHIFT = 0xf,
+       MAC_DIV_CON_MASK = 0x1f,
+
+       RMII_EXTCLK_SHIFT = 4,
+       RMII_EXTCLK_MASK = 1,
+       RMII_EXTCLK_SELECT_INT_DIV_CLK = 0,
+       RMII_EXTCLK_SELECT_EXT_CLK = 1,
+
+       EMAC_PLL_SHIFT = 0,
+       EMAC_PLL_MASK = 0x3,
+       EMAC_PLL_SELECT_NEW = 0x0,
+       EMAC_PLL_SELECT_CODEC = 0x1,
+       EMAC_PLL_SELECT_GENERAL = 0x2,
+};
+
 /* CRU_CLKSEL25_CON */
 enum {
        SPI1_PLL_SHIFT          = 0xf,
@@ -109,6 +133,18 @@ enum {
        SPI0_DIV_MASK           = 0x7f,
 };
 
+/* CRU_CLKSEL37_CON */
+enum {
+       PCLK_CORE_DBG_DIV_SHIFT = 9,
+       PCLK_CORE_DBG_DIV_MASK  = 0x1f,
+
+       ATCLK_CORE_DIV_CON_SHIFT = 4,
+       ATCLK_CORE_DIV_CON_MASK = 0x1f,
+
+       CLK_L2RAM_DIV_SHIFT     = 0,
+       CLK_L2RAM_DIV_MASK      = 7,
+};
+
 /* CRU_CLKSEL39_CON */
 enum {
        ACLK_HEVC_PLL_SHIFT     = 0xe,
@@ -131,35 +167,35 @@ enum {
 
 /* CRU_MODE_CON */
 enum {
-       NPLL_WORK_SHIFT         = 0xe,
-       NPLL_WORK_MASK          = 3,
-       NPLL_WORK_SLOW          = 0,
-       NPLL_WORK_NORMAL,
-       NPLL_WORK_DEEP,
-
-       GPLL_WORK_SHIFT         = 0xc,
-       GPLL_WORK_MASK          = 3,
-       GPLL_WORK_SLOW          = 0,
-       GPLL_WORK_NORMAL,
-       GPLL_WORK_DEEP,
-
-       CPLL_WORK_SHIFT         = 8,
-       CPLL_WORK_MASK          = 3,
-       CPLL_WORK_SLOW          = 0,
-       CPLL_WORK_NORMAL,
-       CPLL_WORK_DEEP,
-
-       DPLL_WORK_SHIFT         = 4,
-       DPLL_WORK_MASK          = 3,
-       DPLL_WORK_SLOW          = 0,
-       DPLL_WORK_NORMAL,
-       DPLL_WORK_DEEP,
-
-       APLL_WORK_SHIFT         = 0,
-       APLL_WORK_MASK          = 3,
-       APLL_WORK_SLOW          = 0,
-       APLL_WORK_NORMAL,
-       APLL_WORK_DEEP,
+       NPLL_MODE_SHIFT         = 0xe,
+       NPLL_MODE_MASK          = 3,
+       NPLL_MODE_SLOW          = 0,
+       NPLL_MODE_NORMAL,
+       NPLL_MODE_DEEP,
+
+       GPLL_MODE_SHIFT         = 0xc,
+       GPLL_MODE_MASK          = 3,
+       GPLL_MODE_SLOW          = 0,
+       GPLL_MODE_NORMAL,
+       GPLL_MODE_DEEP,
+
+       CPLL_MODE_SHIFT         = 8,
+       CPLL_MODE_MASK          = 3,
+       CPLL_MODE_SLOW          = 0,
+       CPLL_MODE_NORMAL,
+       CPLL_MODE_DEEP,
+
+       DPLL_MODE_SHIFT         = 4,
+       DPLL_MODE_MASK          = 3,
+       DPLL_MODE_SLOW          = 0,
+       DPLL_MODE_NORMAL,
+       DPLL_MODE_DEEP,
+
+       APLL_MODE_SHIFT         = 0,
+       APLL_MODE_MASK          = 3,
+       APLL_MODE_SLOW          = 0,
+       APLL_MODE_NORMAL,
+       APLL_MODE_DEEP,
 };
 
 /* CRU_APLL_CON0 */