]> git.sur5r.net Git - u-boot/blobdiff - arch/arm/include/asm/arch-s5pc1xx/cpu.h
Exynos542x: Add and enable get_periph_rate support
[u-boot] / arch / arm / include / asm / arch-s5pc1xx / cpu.h
index b3af8cc782af8ad52ea22acc818c1575ae007e7c..5ae5c871693f76e035ca593bc2f58ed54dc2c018 100644 (file)
@@ -3,31 +3,18 @@
  * Minkyu Kang <mk7.kang@samsung.com>
  * Heungjun Kim <riverful.kim@samsung.com>
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef _S5PC1XX_CPU_H
 #define _S5PC1XX_CPU_H
 
+#define S5P_CPU_NAME           "S5P"
 #define S5PC1XX_ADDR_BASE      0xE0000000
 
-#define S5PC1XX_CLOCK_BASE     0xE0100000
-
 /* S5PC100 */
+#define S5PC100_PRO_ID         0xE0000000
+#define S5PC100_CLOCK_BASE     0xE0100000
 #define S5PC100_GPIO_BASE      0xE0300000
 #define S5PC100_VIC0_BASE      0xE4000000
 #define S5PC100_VIC1_BASE      0xE4100000
@@ -41,6 +28,8 @@
 #define S5PC100_MMC_BASE       0xED800000
 
 /* S5PC110 */
+#define S5PC110_PRO_ID         0xE0000000
+#define S5PC110_CLOCK_BASE     0xE0100000
 #define S5PC110_GPIO_BASE      0xE0200000
 #define S5PC110_PWMTIMER_BASE  0xE2500000
 #define S5PC110_WATCHDOG_BASE  0xE2700000
 #define S5PC110_VIC1_BASE      0xF2100000
 #define S5PC110_VIC2_BASE      0xF2200000
 #define S5PC110_VIC3_BASE      0xF2300000
+#define S5PC110_OTG_BASE       0xEC000000
+#define S5PC110_PHY_BASE       0xEC100000
+#define S5PC110_USB_PHY_CONTROL 0xE010E80C
 
-/* Chip ID */
-#define S5PC1XX_PRO_ID         0xE0000000
 
 #ifndef __ASSEMBLY__
+#include <asm/io.h>
 /* CPU detection macros */
-extern unsigned int s5pc1xx_cpu_id;
+extern unsigned int s5p_cpu_id;
+extern unsigned int s5p_cpu_rev;
+
+static inline int s5p_get_cpu_rev(void)
+{
+       return s5p_cpu_rev;
+}
+
+static inline void s5p_set_cpu_id(void)
+{
+       s5p_cpu_id = readl(S5PC100_PRO_ID);
+       s5p_cpu_rev = s5p_cpu_id & 0x000000FF;
+       s5p_cpu_id = 0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12);
+}
+
+static inline char *s5p_get_cpu_name(void)
+{
+       return S5P_CPU_NAME;
+}
 
 #define IS_SAMSUNG_TYPE(type, id)                      \
 static inline int cpu_is_##type(void)                  \
 {                                                      \
-       return s5pc1xx_cpu_id == id ? 1 : 0;            \
+       return s5p_cpu_id == id ? 1 : 0;                \
 }
 
 IS_SAMSUNG_TYPE(s5pc100, 0xc100)
 IS_SAMSUNG_TYPE(s5pc110, 0xc110)
+
+#define SAMSUNG_BASE(device, base)                             \
+static inline unsigned int samsung_get_base_##device(void)     \
+{                                                              \
+       if (cpu_is_s5pc100())                                   \
+               return S5PC100_##base;                          \
+       else if (cpu_is_s5pc110())                              \
+               return S5PC110_##base;                          \
+       else                                                    \
+               return 0;                                       \
+}
+
+SAMSUNG_BASE(clock, CLOCK_BASE)
+SAMSUNG_BASE(gpio, GPIO_BASE)
+SAMSUNG_BASE(pro_id, PRO_ID)
+SAMSUNG_BASE(mmc, MMC_BASE)
+SAMSUNG_BASE(sromc, SROMC_BASE)
+SAMSUNG_BASE(timer, PWMTIMER_BASE)
+SAMSUNG_BASE(uart, UART_BASE)
+SAMSUNG_BASE(watchdog, WATCHDOG_BASE)
 #endif
 
 #endif /* _S5PC1XX_CPU_H */