u32 mipi_pll_cfg; /* 0x40 MIPI pll control */
u32 pll9_cfg; /* 0x44 pll9 control */
u32 pll10_cfg; /* 0x48 pll10 control */
- u32 reserved8;
+ u32 pll11_cfg; /* 0x4c pll11 (ddr1) control (A33 only) */
u32 cpu_axi_cfg; /* 0x50 CPU/AXI divide ratio */
u32 ahb1_apb1_div; /* 0x54 AHB1/APB1 divide ratio */
u32 apb2_div; /* 0x58 APB2 divide ratio */
u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */
u32 apb1_gate; /* 0x68 apb1 module clock gating */
u32 apb2_gate; /* 0x6c apb2 module clock gating */
- u32 reserved9[4];
+ u32 bus_gate4; /* 0x70 gate 4 module clock gating */
+ u8 res3[0xc];
u32 nand0_clk_cfg; /* 0x80 nand0 clock control */
u32 nand1_clk_cfg; /* 0x84 nand1 clock control */
u32 sd0_clk_cfg; /* 0x88 sd0 clock control */
u32 reserved12[7];
u32 mdfs_clk_cfg; /* 0xf0 MDFS clock control */
u32 dram_clk_cfg; /* 0xf4 DRAM configuration clock control */
- u32 reserved13[2];
+ u32 dram_pll_cfg; /* 0xf8 PLL_DDR cfg register, A33 only */
+ u32 mbus_reset; /* 0xfc MBUS reset control, A33 only */
u32 dram_clk_gate; /* 0x100 DRAM module gating */
u32 be0_clk_cfg; /* 0x104 BE0 module clock */
u32 be1_clk_cfg; /* 0x108 BE1 module clock */
u32 mipi_pattern_cfg; /* 0x2a0 MIPI Pattern config */
u32 pll9_pattern_cfg; /* 0x2a4 PLL9 Pattern config */
u32 pll10_pattern_cfg; /* 0x2a8 PLL10 Pattern config */
- u32 reserved22[5];
+ u32 pll11_pattern_cfg0; /* 0x2ac PLL11 Pattern config0, A33 only */
+ u32 pll11_pattern_cfg1; /* 0x2b0 PLL11 Pattern config0, A33 only */
+ u32 reserved22[3];
u32 ahb_reset0_cfg; /* 0x2c0 AHB1 Reset 0 config */
u32 ahb_reset1_cfg; /* 0x2c4 AHB1 Reset 1 config */
u32 ahb_reset2_cfg; /* 0x2c8 AHB1 Reset 2 config */
u32 apb1_reset_cfg; /* 0x2d0 APB1 Reset config */
u32 reserved24;
u32 apb2_reset_cfg; /* 0x2d8 APB2 Reset config */
+ u32 reserved25[5];
+ u32 ccu_sec_switch; /* 0x2f0 CCU Security Switch, H3 only */
};
/* apb2 bit field */
#define CCM_PLL1_CTRL_P(n) (((n) & 0x3) << 16)
#define CCM_PLL1_CTRL_EN (0x1 << 31)
+#define CCM_PLL3_CTRL_M_SHIFT 0
+#define CCM_PLL3_CTRL_M_MASK (0xf << CCM_PLL3_CTRL_M_SHIFT)
#define CCM_PLL3_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
+#define CCM_PLL3_CTRL_N_SHIFT 8
+#define CCM_PLL3_CTRL_N_MASK (0x7f << CCM_PLL3_CTRL_N_SHIFT)
#define CCM_PLL3_CTRL_N(n) ((((n) - 1) & 0x7f) << 8)
#define CCM_PLL3_CTRL_INTEGER_MODE (0x1 << 24)
#define CCM_PLL3_CTRL_EN (0x1 << 31)
#define CCM_PLL6_CTRL_N_MASK (0x1f << CCM_PLL6_CTRL_N_SHIFT)
#define CCM_PLL6_CTRL_K_SHIFT 4
#define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT)
-
-#define AHB1_ABP1_DIV_DEFAULT 0x00002020
+#define CCM_PLL6_CTRL_LOCK (1 << 28)
+
+#define CCM_MIPI_PLL_CTRL_M_SHIFT 0
+#define CCM_MIPI_PLL_CTRL_M_MASK (0xf << CCM_MIPI_PLL_CTRL_M_SHIFT)
+#define CCM_MIPI_PLL_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
+#define CCM_MIPI_PLL_CTRL_K_SHIFT 4
+#define CCM_MIPI_PLL_CTRL_K_MASK (0x3 << CCM_MIPI_PLL_CTRL_K_SHIFT)
+#define CCM_MIPI_PLL_CTRL_K(n) ((((n) - 1) & 0x3) << 4)
+#define CCM_MIPI_PLL_CTRL_N_SHIFT 8
+#define CCM_MIPI_PLL_CTRL_N_MASK (0xf << CCM_MIPI_PLL_CTRL_N_SHIFT)
+#define CCM_MIPI_PLL_CTRL_N(n) ((((n) - 1) & 0xf) << 8)
+#define CCM_MIPI_PLL_CTRL_LDO_EN (0x3 << 22)
+#define CCM_MIPI_PLL_CTRL_EN (0x1 << 31)
+
+#define CCM_PLL11_CTRL_N(n) ((((n) - 1) & 0x3f) << 8)
+#define CCM_PLL11_CTRL_SIGMA_DELTA_EN (0x1 << 24)
+#define CCM_PLL11_CTRL_UPD (0x1 << 30)
+#define CCM_PLL11_CTRL_EN (0x1 << 31)
+
+#if defined(CONFIG_MACH_SUN50I)
+/* AHB1=100MHz failsafe setup from the FEL mode, usable with PMIC defaults */
+#define AHB1_ABP1_DIV_DEFAULT 0x00003190 /* AHB1=PLL6/6,APB1=AHB1/2 */
+#else
+#define AHB1_ABP1_DIV_DEFAULT 0x00003180 /* AHB1=PLL6/3,APB1=AHB1/2 */
+#endif
#define AXI_GATE_OFFSET_DRAM 0
/* ahb_gate0 offsets */
#define AHB_GATE_OFFSET_USB_OHCI1 30
#define AHB_GATE_OFFSET_USB_OHCI0 29
+#ifdef CONFIG_MACH_SUN8I_H3
+/*
+ * These are EHCI1 - EHCI3 in the datasheet (EHCI0 is for the OTG) we call
+ * them 0 - 2 like they were called on older SoCs.
+ */
+#define AHB_GATE_OFFSET_USB_EHCI2 27
+#define AHB_GATE_OFFSET_USB_EHCI1 26
+#define AHB_GATE_OFFSET_USB_EHCI0 25
+#else
#define AHB_GATE_OFFSET_USB_EHCI1 27
#define AHB_GATE_OFFSET_USB_EHCI0 26
+#endif
#define AHB_GATE_OFFSET_USB0 24
#define AHB_GATE_OFFSET_MCTL 14
#define AHB_GATE_OFFSET_GMAC 17
+#define AHB_GATE_OFFSET_NAND0 13
+#define AHB_GATE_OFFSET_NAND1 12
#define AHB_GATE_OFFSET_MMC3 11
#define AHB_GATE_OFFSET_MMC2 10
#define AHB_GATE_OFFSET_MMC1 9
#define AHB_GATE_OFFSET_MMC0 8
#define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n))
+#define AHB_GATE_OFFSET_DMA 6
#define AHB_GATE_OFFSET_SS 5
/* ahb_gate1 offsets */
#define AHB_GATE_OFFSET_DRC0 25
+#define AHB_GATE_OFFSET_DE_FE0 14
#define AHB_GATE_OFFSET_DE_BE0 12
#define AHB_GATE_OFFSET_HDMI 11
#define AHB_GATE_OFFSET_LCD1 5
#define CCM_USB_CTRL_PHY0_RST (0x1 << 0)
#define CCM_USB_CTRL_PHY1_RST (0x1 << 1)
#define CCM_USB_CTRL_PHY2_RST (0x1 << 2)
+#define CCM_USB_CTRL_PHY3_RST (0x1 << 3)
/* There is no global phy clk gate on sun6i, define as 0 */
#define CCM_USB_CTRL_PHYGATE 0
#define CCM_USB_CTRL_PHY0_CLK (0x1 << 8)
#define CCM_USB_CTRL_PHY1_CLK (0x1 << 9)
#define CCM_USB_CTRL_PHY2_CLK (0x1 << 10)
+#define CCM_USB_CTRL_PHY3_CLK (0x1 << 11)
+#ifdef CONFIG_MACH_SUN8I_H3
+/*
+ * These are OHCI1 - OHCI3 in the datasheet (OHCI0 is for the OTG) we call
+ * them 0 - 2 like they were called on older SoCs.
+ */
+#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 17)
+#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 18)
+#define CCM_USB_CTRL_OHCI2_CLK (0x1 << 19)
+#else
+#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16)
+#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17)
+#endif
#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0
#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1
#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2
#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2)
#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2)
+#define CCM_GMAC_CTRL_RX_CLK_DELAY(x) ((x) << 5)
+#define CCM_GMAC_CTRL_TX_CLK_DELAY(x) ((x) << 10)
#define MDFS_CLK_DEFAULT 0x81000002 /* PLL6 / 3 */
+#define CCM_DRAMCLK_CFG_DIV(x) ((x - 1) << 0)
+#define CCM_DRAMCLK_CFG_DIV_MASK (0xf << 0)
#define CCM_DRAMCLK_CFG_DIV0(x) ((x - 1) << 8)
#define CCM_DRAMCLK_CFG_DIV0_MASK (0xf << 8)
+#define CCM_DRAMCLK_CFG_SRC_PLL5 (0x0 << 20)
+#define CCM_DRAMCLK_CFG_SRC_PLL6x2 (0x1 << 20)
+#define CCM_DRAMCLK_CFG_SRC_MASK (0x3 << 20)
#define CCM_DRAMCLK_CFG_UPD (0x1 << 16)
#define CCM_DRAMCLK_CFG_RST (0x1 << 31)
+#define CCM_DRAMPLL_CFG_SRC_PLL5 (0x0 << 16) /* Select PLL5 (DDR0) */
+#define CCM_DRAMPLL_CFG_SRC_PLL11 (0x1 << 16) /* Select PLL11 (DDR1) */
+#define CCM_DRAMPLL_CFG_SRC_MASK (0x1 << 16)
+
+#define CCM_MBUS_RESET_RESET (0x1 << 31)
+
+#define CCM_DRAM_GATE_OFFSET_DE_FE0 24
+#define CCM_DRAM_GATE_OFFSET_DE_FE1 25
#define CCM_DRAM_GATE_OFFSET_DE_BE0 26
+#define CCM_DRAM_GATE_OFFSET_DE_BE1 27
#define CCM_LCD_CH0_CTRL_PLL3 (0 << 24)
#define CCM_LCD_CH0_CTRL_PLL7 (1 << 24)
#define CCM_LCD_CH0_CTRL_GATE (0x1 << 31)
#define CCM_LCD_CH1_CTRL_M(n) ((((n) - 1) & 0xf) << 0)
+#define CCM_LCD_CH1_CTRL_HALF_SCLK1 0 /* no seperate sclk1 & 2 on sun6i */
#define CCM_LCD_CH1_CTRL_PLL3 (0 << 24)
#define CCM_LCD_CH1_CTRL_PLL7 (1 << 24)
#define CCM_LCD_CH1_CTRL_PLL3_2X (2 << 24)
#define CCM_HDMI_CTRL_DDC_GATE (0x1 << 30)
#define CCM_HDMI_CTRL_GATE (0x1 << 31)
-#ifndef CONFIG_MACH_SUN8I
-#define MBUS_CLK_DEFAULT 0x81000001 /* PLL6 / 2 */
-#else
+#if defined(CONFIG_MACH_SUN50I)
+#define MBUS_CLK_DEFAULT 0x81000002 /* PLL6x2 / 3 */
+#elif defined(CONFIG_MACH_SUN8I)
#define MBUS_CLK_DEFAULT 0x81000003 /* PLL6 / 4 */
+#else
+#define MBUS_CLK_DEFAULT 0x81000001 /* PLL6 / 2 */
#endif
+#define MBUS_CLK_GATE (0x1 << 31)
#define CCM_PLL5_PATTERN 0xd1303333
+#define CCM_PLL11_PATTERN 0xf5860000
/* ahb_reset0 offsets */
#define AHB_RESET_OFFSET_GMAC 17
#define AHB_RESET_OFFSET_SS 5
/* ahb_reset1 offsets */
+#define AHB_RESET_OFFSET_SAT 26
#define AHB_RESET_OFFSET_DRC0 25
+#define AHB_RESET_OFFSET_DE_FE0 14
#define AHB_RESET_OFFSET_DE_BE0 12
#define AHB_RESET_OFFSET_HDMI 11
#define AHB_RESET_OFFSET_LCD1 5
#define AHB_RESET_OFFSET_LCD0 4
+/* ahb_reset2 offsets */
+#define AHB_RESET_OFFSET_EPHY 2
+#define AHB_RESET_OFFSET_LVDS 0
+
/* apb2 reset */
#define APB2_RESET_UART_SHIFT (16)
#define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT)
#define CCM_DE_CTRL_PLL10 (5 << 24)
#define CCM_DE_CTRL_GATE (1 << 31)
+/* CCU security switch, H3 only */
+#define CCM_SEC_SWITCH_MBUS_NONSEC (1 << 2)
+#define CCM_SEC_SWITCH_BUS_NONSEC (1 << 1)
+#define CCM_SEC_SWITCH_PLL_NONSEC (1 << 0)
+
+#ifndef __ASSEMBLY__
+void clock_set_pll1(unsigned int hz);
+void clock_set_pll3(unsigned int hz);
void clock_set_pll5(unsigned int clk, bool sigma_delta_enable);
+void clock_set_pll11(unsigned int clk, bool sigma_delta_enable);
+void clock_set_mipi_pll(unsigned int hz);
+unsigned int clock_get_pll3(void);
+unsigned int clock_get_pll6(void);
+unsigned int clock_get_mipi_pll(void);
+#endif
#endif /* _SUNXI_CLOCK_SUN6I_H */
projects / u-boot / blobdiff