Merge branch 'master' of git://git.denx.de/u-boot-tegra

[u-boot] / arch / arm / include / asm / arch-tegra / clock.h

diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h
index f9dd3c817d13efb76de90fafbb7aa9e78d9326ea..e56031d1afa7e8bd5508447be3e2c16aa0d9417b 100644 (file)
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -16,6 +16,8 @@ enum clock_osc_freq {
        CLOCK_OSC_FREQ_19_2,
        CLOCK_OSC_FREQ_12_0,
        CLOCK_OSC_FREQ_26_0,
+       CLOCK_OSC_FREQ_38_4,
+       CLOCK_OSC_FREQ_48_0,
 
        CLOCK_OSC_FREQ_COUNT,
 };
@@ -42,6 +44,9 @@ enum {
 /* return the current oscillator clock frequency */
 enum clock_osc_freq clock_get_osc_freq(void);
 
+/* return the clk_m frequency */
+unsigned int clk_m_get_rate(unsigned int parent_rate);
+
 /**
  * Start PLL using the provided configuration parameters.
  *
@@ -336,6 +341,27 @@ void arch_timer_init(void);
 
 void tegra30_set_up_pllp(void);
 
+/* Number of PLL-based clocks (i.e. not OSC, MCLK or 32KHz) */
+#define CLOCK_ID_PLL_COUNT     (CLOCK_ID_COUNT - 3)
+
+struct clk_pll_info {
+       u32     m_shift:5;      /* DIVM_SHIFT */
+       u32     n_shift:5;      /* DIVN_SHIFT */
+       u32     p_shift:5;      /* DIVP_SHIFT */
+       u32     kcp_shift:5;    /* KCP/cpcon SHIFT */
+       u32     kvco_shift:5;   /* KVCO/lfcon SHIFT */
+       u32     lock_ena:6;     /* LOCK_ENABLE/EN_LOCKDET shift */
+       u32     rsvd:1;
+       u32     m_mask:10;      /* DIVM_MASK */
+       u32     n_mask:12;      /* DIVN_MASK */
+       u32     p_mask:10;      /* DIVP_MASK or VCO_MASK */
+       u32     kcp_mask:10;    /* KCP/CPCON MASK */
+       u32     kvco_mask:10;   /* KVCO/LFCON MASK */
+       u32     lock_det:6;     /* LOCK_DETECT/LOCKED shift */
+       u32     rsvd2:6;
+};
+extern struct clk_pll_info tegra_pll_info_table[CLOCK_ID_PLL_COUNT];
+
 /**
  * Enable output clock for external peripherals
  *