]> git.sur5r.net Git - u-boot/blobdiff - arch/arm/include/asm/arch-vf610/crm_regs.h
imx: mx6: fix reg base address when runtime usage
[u-boot] / arch / arm / include / asm / arch-vf610 / crm_regs.h
index bc6db2a5a55d5de37cc283be4972148611aa1827..a46e396f1d9c16573d5339b6b9c59b5c4c6810bd 100644 (file)
@@ -189,6 +189,8 @@ struct anadig_reg {
 #define CCM_REG_CTRL_MASK                      0xffffffff
 #define CCM_CCGR0_UART0_CTRL_MASK               (0x3 << 14)
 #define CCM_CCGR0_UART1_CTRL_MASK              (0x3 << 16)
+#define CCM_CCGR0_DSPI0_CTRL_MASK              (0x3 << 24)
+#define CCM_CCGR0_DSPI1_CTRL_MASK              (0x3 << 26)
 #define CCM_CCGR1_USBC0_CTRL_MASK       (0x3 << 8)
 #define CCM_CCGR1_PIT_CTRL_MASK                        (0x3 << 14)
 #define CCM_CCGR1_WDOGA5_CTRL_MASK             (0x3 << 28)
@@ -205,13 +207,18 @@ struct anadig_reg {
 #define CCM_CCGR4_CCM_CTRL_MASK                        (0x3 << 22)
 #define CCM_CCGR4_GPC_CTRL_MASK                        (0x3 << 24)
 #define CCM_CCGR4_I2C0_CTRL_MASK               (0x3 << 12)
+#define CCM_CCGR4_I2C1_CTRL_MASK               (0x3 << 14)
 #define CCM_CCGR6_OCOTP_CTRL_MASK              (0x3 << 10)
+#define CCM_CCGR6_DSPI2_CTRL_MASK              (0x3 << 24)
+#define CCM_CCGR6_DSPI3_CTRL_MASK              (0x3 << 26)
 #define CCM_CCGR6_DDRMC_CTRL_MASK              (0x3 << 28)
 #define CCM_CCGR7_SDHC1_CTRL_MASK              (0x3 << 4)
 #define CCM_CCGR7_USBC1_CTRL_MASK       (0x3 << 8)
 #define CCM_CCGR9_FEC0_CTRL_MASK               0x3
 #define CCM_CCGR9_FEC1_CTRL_MASK               (0x3 << 2)
 #define CCM_CCGR10_NFC_CTRL_MASK               0x3
+#define CCM_CCGR10_I2C2_CTRL_MASK              (0x3 << 12)
+#define CCM_CCGR10_I2C3_CTRL_MASK              (0x3 << 14)
 
 #define ANADIG_PLL7_CTRL_BYPASS         (1 << 16)
 #define ANADIG_PLL7_CTRL_ENABLE         (1 << 13)