Merge branch 'master' of git://git.denx.de/u-boot

[u-boot] / arch / arm / include / asm / arch-vf610 / crm_regs.h

diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h
index 5256624adf4691c33d68395faef0ab06594de7fc..a46e396f1d9c16573d5339b6b9c59b5c4c6810bd 100644 (file)
--- a/arch/arm/include/asm/arch-vf610/crm_regs.h
+++ b/arch/arm/include/asm/arch-vf610/crm_regs.h
@@ -156,14 +156,27 @@ struct anadig_reg {
 #define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET       18
 #define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK         (0x3 << 18)
 #define CCM_CSCMR1_ESDHC1_CLK_SEL(v)           (((v) & 0x3) << 18)
+#define CCM_CSCMR1_NFC_CLK_SEL_OFFSET          12
+#define CCM_CSCMR1_NFC_CLK_SEL_MASK            (0x3 << 12)
+#define CCM_CSCMR1_NFC_CLK_SEL(v)              (((v) & 0x3) << 12)
 
 #define CCM_CSCDR1_RMII_CLK_EN                 (1 << 24)
 
+#define CCM_CSCDR2_NFC_EN                      (1 << 9)
+#define CCM_CSCDR2_NFC_FRAC_DIV_EN             (1 << 13)
+#define CCM_CSCDR2_NFC_CLK_INV                 (1 << 14)
+#define CCM_CSCDR2_NFC_FRAC_DIV_OFFSET         4
+#define CCM_CSCDR2_NFC_FRAC_DIV_MASK           (0xf << 4)
+#define CCM_CSCDR2_NFC_FRAC_DIV(v)             (((v) & 0xf) << 4)
+
 #define CCM_CSCDR2_ESDHC1_EN                   (1 << 29)
 #define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET       20
 #define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK         (0xf << 20)
 #define CCM_CSCDR2_ESDHC1_CLK_DIV(v)           (((v) & 0xf) << 20)
 
+#define CCM_CSCDR3_NFC_PRE_DIV_OFFSET          13
+#define CCM_CSCDR3_NFC_PRE_DIV_MASK            (0x7 << 13)
+#define CCM_CSCDR3_NFC_PRE_DIV(v)              (((v) & 0x7) << 13)
 #define CCM_CSCDR3_QSPI0_EN                    (1 << 4)
 #define CCM_CSCDR3_QSPI0_DIV(v)                        ((v) << 3)
 #define CCM_CSCDR3_QSPI0_X2_DIV(v)             ((v) << 2)
@@ -176,6 +189,9 @@ struct anadig_reg {
 #define CCM_REG_CTRL_MASK                      0xffffffff
 #define CCM_CCGR0_UART0_CTRL_MASK               (0x3 << 14)
 #define CCM_CCGR0_UART1_CTRL_MASK              (0x3 << 16)
+#define CCM_CCGR0_DSPI0_CTRL_MASK              (0x3 << 24)
+#define CCM_CCGR0_DSPI1_CTRL_MASK              (0x3 << 26)
+#define CCM_CCGR1_USBC0_CTRL_MASK       (0x3 << 8)
 #define CCM_CCGR1_PIT_CTRL_MASK                        (0x3 << 14)
 #define CCM_CCGR1_WDOGA5_CTRL_MASK             (0x3 << 28)
 #define CCM_CCGR2_QSPI0_CTRL_MASK              (0x3 << 8)
@@ -186,20 +202,36 @@ struct anadig_reg {
 #define CCM_CCGR2_PORTD_CTRL_MASK              (0x3 << 24)
 #define CCM_CCGR2_PORTE_CTRL_MASK              (0x3 << 26)
 #define CCM_CCGR3_ANADIG_CTRL_MASK             0x3
+#define CCM_CCGR3_SCSC_CTRL_MASK        (0x3 << 4)
 #define CCM_CCGR4_WKUP_CTRL_MASK               (0x3 << 20)
 #define CCM_CCGR4_CCM_CTRL_MASK                        (0x3 << 22)
 #define CCM_CCGR4_GPC_CTRL_MASK                        (0x3 << 24)
 #define CCM_CCGR4_I2C0_CTRL_MASK               (0x3 << 12)
+#define CCM_CCGR4_I2C1_CTRL_MASK               (0x3 << 14)
 #define CCM_CCGR6_OCOTP_CTRL_MASK              (0x3 << 10)
+#define CCM_CCGR6_DSPI2_CTRL_MASK              (0x3 << 24)
+#define CCM_CCGR6_DSPI3_CTRL_MASK              (0x3 << 26)
 #define CCM_CCGR6_DDRMC_CTRL_MASK              (0x3 << 28)
 #define CCM_CCGR7_SDHC1_CTRL_MASK              (0x3 << 4)
+#define CCM_CCGR7_USBC1_CTRL_MASK       (0x3 << 8)
 #define CCM_CCGR9_FEC0_CTRL_MASK               0x3
 #define CCM_CCGR9_FEC1_CTRL_MASK               (0x3 << 2)
+#define CCM_CCGR10_NFC_CTRL_MASK               0x3
+#define CCM_CCGR10_I2C2_CTRL_MASK              (0x3 << 12)
+#define CCM_CCGR10_I2C3_CTRL_MASK              (0x3 << 14)
 
+#define ANADIG_PLL7_CTRL_BYPASS         (1 << 16)
+#define ANADIG_PLL7_CTRL_ENABLE         (1 << 13)
+#define ANADIG_PLL7_CTRL_POWERDOWN      (1 << 12)
+#define ANADIG_PLL7_CTRL_DIV_SELECT     (1 << 1)
 #define ANADIG_PLL5_CTRL_BYPASS                 (1 << 16)
 #define ANADIG_PLL5_CTRL_ENABLE                 (1 << 13)
 #define ANADIG_PLL5_CTRL_POWERDOWN              (1 << 12)
 #define ANADIG_PLL5_CTRL_DIV_SELECT            1
+#define ANADIG_PLL3_CTRL_BYPASS         (1 << 16)
+#define ANADIG_PLL3_CTRL_ENABLE         (1 << 13)
+#define ANADIG_PLL3_CTRL_POWERDOWN      (1 << 12)
+#define ANADIG_PLL3_CTRL_DIV_SELECT     (1 << 1)
 #define ANADIG_PLL2_CTRL_ENABLE                        (1 << 13)
 #define ANADIG_PLL2_CTRL_POWERDOWN             (1 << 12)
 #define ANADIG_PLL2_CTRL_DIV_SELECT            1