Merge branch 'master' of git://git.denx.de/u-boot-socfpga

[u-boot] / arch / arm / include / asm / arch-vf610 / imx-regs.h

diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h
index 202198133cfbc560cdaf6e6ba46d54fc71ff2534..975832343316947ec13aca511cc39a58e7e250d0 100644 (file)
--- a/arch/arm/include/asm/arch-vf610/imx-regs.h
+++ b/arch/arm/include/asm/arch-vf610/imx-regs.h
@@ -75,12 +75,20 @@
 #define ESAI_FIFO_BASE_ADDR    (AIPS0_BASE_ADDR + 0x00063000)
 #define WDOG_BASE_ADDR         (AIPS0_BASE_ADDR + 0x00065000)
 #define I2C1_BASE_ADDR         (AIPS0_BASE_ADDR + 0x00066000)
+#define I2C2_BASE_ADDR         (AIPS0_BASE_ADDR + 0x00067000)
+#define I2C3_BASE_ADDR         (AIPS0_BASE_ADDR + 0x000E6000)
+#define I2C4_BASE_ADDR         (AIPS0_BASE_ADDR + 0x000E7000)
 #define WKUP_BASE_ADDR         (AIPS0_BASE_ADDR + 0x0006A000)
 #define CCM_BASE_ADDR          (AIPS0_BASE_ADDR + 0x0006B000)
 #define GPC_BASE_ADDR          (AIPS0_BASE_ADDR + 0x0006C000)
 #define VREG_DIG_BASE_ADDR     (AIPS0_BASE_ADDR + 0x0006D000)
 #define SRC_BASE_ADDR          (AIPS0_BASE_ADDR + 0x0006E000)
 #define CMU_BASE_ADDR          (AIPS0_BASE_ADDR + 0x0006F000)
+#define GPIO0_BASE_ADDR                (AIPS0_BASE_ADDR + 0x000FF000)
+#define GPIO1_BASE_ADDR                (AIPS0_BASE_ADDR + 0x000FF040)
+#define GPIO2_BASE_ADDR                (AIPS0_BASE_ADDR + 0x000FF080)
+#define GPIO3_BASE_ADDR                (AIPS0_BASE_ADDR + 0x000FF0C0)
+#define GPIO4_BASE_ADDR                (AIPS0_BASE_ADDR + 0x000FF100)
 
 /* AIPS 1 */
 #define OCOTP_BASE_ADDR                (AIPS1_BASE_ADDR + 0x00025000)
@@ -140,7 +148,7 @@
 #define DDRMC_CR18_TCKE(v)                             ((v) & 0x7)
 #define DDRMC_CR20_AP_EN                               (1 << 24)
 #define DDRMC_CR21_TRCD_INT(v)                         (((v) & 0xff) << 16)
-#define DDRMC_CR21_TRAS_LOCKOUT                                (1 << 8)
+#define DDRMC_CR21_TRAS_LOCKOUT(v)                     ((v) << 8)
 #define DDRMC_CR21_CCMAP_EN                            1
 #define DDRMC_CR22_TDAL(v)                             (((v) & 0x3f) << 16)
 #define DDRMC_CR23_BSTLEN(v)                           (((v) & 0x7) << 24)
@@ -192,8 +200,8 @@
 #define DDRMC_CR78_BUR_ON_FLY_BIT(v)                   ((v) & 0xf)
 #define DDRMC_CR79_CTLUPD_AREF(v)                      (((v) & 0x1) << 24)
 #define DDRMC_CR82_INT_MASK                            0x10000000
-#define DDRMC_CR87_ODT_WR_MAPCS0                       (1 << 24)
-#define DDRMC_CR87_ODT_RD_MAPCS0                       (1 << 16)
+#define DDRMC_CR87_ODT_WR_MAPCS0(v)                    ((v) << 24)
+#define DDRMC_CR87_ODT_RD_MAPCS0(v)                    ((v) << 16)
 #define DDRMC_CR88_TODTL_CMD(v)                                (((v) & 0x1f) << 16)
 #define DDRMC_CR89_AODT_RWSMCS(v)                      ((v) & 0xf)
 #define DDRMC_CR91_R2W_SMCSDL(v)                       (((v) & 0x7) << 16)