ARM: atmel: spl: add saic to aic redirect function

[u-boot] / arch / arm / include / asm / armv7.h

diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
index 0f7cbbfc12ea3c6dcaa8719f2136f2350fbcb906..a13da23cf1726c6b2c4b4d22b820dd959060dffa 100644 (file)
--- a/arch/arm/include/asm/armv7.h
+++ b/arch/arm/include/asm/armv7.h
@@ -18,6 +18,22 @@
 #define MIDR_CORTEX_A15_R0P0   0x410FC0F0
 #define MIDR_CORTEX_A15_R2P2   0x412FC0F2
 
+/* Cortex-A7 revisions */
+#define MIDR_CORTEX_A7_R0P0    0x410FC070
+
+#define MIDR_PRIMARY_PART_MASK 0xFF0FFFF0
+
+/* ID_PFR1 feature fields */
+#define CPUID_ARM_SEC_SHIFT            4
+#define CPUID_ARM_SEC_MASK             (0xF << CPUID_ARM_SEC_SHIFT)
+#define CPUID_ARM_VIRT_SHIFT           12
+#define CPUID_ARM_VIRT_MASK            (0xF << CPUID_ARM_VIRT_SHIFT)
+#define CPUID_ARM_GENTIMER_SHIFT       16
+#define CPUID_ARM_GENTIMER_MASK                (0xF << CPUID_ARM_GENTIMER_SHIFT)
+
+/* valid bits in CBAR register / PERIPHBASE value */
+#define CBAR_MASK                      0xFFFF8000
+
 /* CCSIDR */
 #define CCSIDR_LINE_SIZE_OFFSET                0
 #define CCSIDR_LINE_SIZE_MASK          0x7
@@ -60,6 +76,23 @@ void v7_outer_cache_inval_all(void);
 void v7_outer_cache_flush_range(u32 start, u32 end);
 void v7_outer_cache_inval_range(u32 start, u32 end);
 
+#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+
+int armv7_init_nonsec(void);
+int armv7_update_dt(void *fdt);
+bool armv7_boot_nonsec(void);
+
+/* defined in assembly file */
+unsigned int _nonsec_init(void);
+void _do_nonsec_entry(void *target_pc, unsigned long r0,
+                     unsigned long r1, unsigned long r2);
+void _smp_pen(void);
+
+extern char __secure_start[];
+extern char __secure_end[];
+
+#endif /* CONFIG_ARMV7_NONSEC || CONFIG_ARMV7_VIRT */
+
 #endif /* ! __ASSEMBLY__ */
 
 #endif