#define MIDR_CORTEX_A9_R0P1 0x410FC091
#define MIDR_CORTEX_A9_R1P2 0x411FC092
#define MIDR_CORTEX_A9_R1P3 0x411FC093
+#define MIDR_CORTEX_A9_R2P10 0x412FC09A
+
+/* Cortex-A15 revisions */
+#define MIDR_CORTEX_A15_R0P0 0x410FC0F0
/* CCSIDR */
#define CCSIDR_LINE_SIZE_OFFSET 0