board: stm32: switch to DM STM32 timer

[u-boot] / arch / arm / include / asm / armv8 / mmu.h

diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 2e2a3a8226d9a6c37fd3336f907e43a26e5d39aa..765914c7e269f03adf1d1d9ead59bd21d2f86ee8 100644 (file)
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -8,33 +8,16 @@
 #ifndef _ASM_ARMV8_MMU_H_
 #define _ASM_ARMV8_MMU_H_
 
-#ifdef __ASSEMBLY__
-#define _AC(X, Y)      X
-#else
-#define _AC(X, Y)      (X##Y)
-#endif
-
-#define UL(x)          _AC(x, UL)
-
-/***************************************************************/
 /*
- * The following definitions are related each other, shoud be
- * calculated specifically.
+ * block/section address mask and size definitions.
  */
-#define VA_BITS                        (42)    /* 42 bits virtual address */
 
 /* PAGE_SHIFT determines the page size */
 #undef  PAGE_SIZE
-#define PAGE_SHIFT             16
+#define PAGE_SHIFT             12
 #define PAGE_SIZE              (1 << PAGE_SHIFT)
-#define PAGE_MASK              (~(PAGE_SIZE-1))
+#define PAGE_MASK              (~(PAGE_SIZE - 1))
 
-/*
- * section address mask and size definitions.
- */
-#define SECTION_SHIFT          29
-#define SECTION_SIZE           (UL(1) << SECTION_SHIFT)
-#define SECTION_MASK           (~(SECTION_SIZE-1))
 /***************************************************************/
 
 /*
@@ -46,39 +29,51 @@
 #define MT_NORMAL_NC           3
 #define MT_NORMAL              4
 
-#define MEMORY_ATTRIBUTES      ((0x00 << (MT_DEVICE_NGNRNE*8)) |       \
-                               (0x04 << (MT_DEVICE_NGNRE*8)) |         \
-                               (0x0c << (MT_DEVICE_GRE*8)) |           \
-                               (0x44 << (MT_NORMAL_NC*8)) |            \
-                               (UL(0xff) << (MT_NORMAL*8)))
+#define MEMORY_ATTRIBUTES      ((0x00 << (MT_DEVICE_NGNRNE * 8)) |     \
+                               (0x04 << (MT_DEVICE_NGNRE * 8))   |     \
+                               (0x0c << (MT_DEVICE_GRE * 8))     |     \
+                               (0x44 << (MT_NORMAL_NC * 8))      |     \
+                               (UL(0xff) << (MT_NORMAL * 8)))
 
 /*
  * Hardware page table definitions.
  *
- * Level 2 descriptor (PMD).
  */
-#define PMD_TYPE_MASK          (3 << 0)
-#define PMD_TYPE_FAULT         (0 << 0)
-#define PMD_TYPE_TABLE         (3 << 0)
-#define PMD_TYPE_SECT          (1 << 0)
+
+#define PTE_TYPE_MASK          (3 << 0)
+#define PTE_TYPE_FAULT         (0 << 0)
+#define PTE_TYPE_TABLE         (3 << 0)
+#define PTE_TYPE_PAGE          (3 << 0)
+#define PTE_TYPE_BLOCK         (1 << 0)
+#define PTE_TYPE_VALID         (1 << 0)
+
+#define PTE_TABLE_PXN          (1UL << 59)
+#define PTE_TABLE_XN           (1UL << 60)
+#define PTE_TABLE_AP           (1UL << 61)
+#define PTE_TABLE_NS           (1UL << 63)
 
 /*
- * Section
+ * Block
  */
-#define PMD_SECT_NS            (1 << 5)
-#define PMD_SECT_NON_SHARE     (0 << 8)
-#define PMD_SECT_OUTER_SHARE   (2 << 8)
-#define PMD_SECT_INNER_SHARE   (3 << 8)
-#define PMD_SECT_AF            (1 << 10)
-#define PMD_SECT_NG            (1 << 11)
-#define PMD_SECT_PXN           (UL(1) << 53)
-#define PMD_SECT_UXN           (UL(1) << 54)
+#define PTE_BLOCK_MEMTYPE(x)   ((x) << 2)
+#define PTE_BLOCK_NS            (1 << 5)
+#define PTE_BLOCK_NON_SHARE    (0 << 8)
+#define PTE_BLOCK_OUTER_SHARE  (2 << 8)
+#define PTE_BLOCK_INNER_SHARE  (3 << 8)
+#define PTE_BLOCK_AF           (1 << 10)
+#define PTE_BLOCK_NG           (1 << 11)
+#define PTE_BLOCK_PXN          (UL(1) << 53)
+#define PTE_BLOCK_UXN          (UL(1) << 54)
 
 /*
  * AttrIndx[2:0]
  */
 #define PMD_ATTRINDX(t)                ((t) << 2)
 #define PMD_ATTRINDX_MASK      (7 << 2)
+#define PMD_ATTRMASK           (PTE_BLOCK_PXN          | \
+                                PTE_BLOCK_UXN          | \
+                                PMD_ATTRINDX_MASK      | \
+                                PTE_TYPE_VALID)
 
 /*
  * TCR flags.
@@ -100,29 +95,13 @@
 #define TCR_TG0_4K             (0 << 14)
 #define TCR_TG0_64K            (1 << 14)
 #define TCR_TG0_16K            (2 << 14)
-#define TCR_EL1_IPS_BITS       (UL(3) << 32)   /* 42 bits physical address */
-#define TCR_EL2_IPS_BITS       (3 << 16)       /* 42 bits physical address */
-#define TCR_EL3_IPS_BITS       (3 << 16)       /* 42 bits physical address */
-
-/* PTWs cacheable, inner/outer WBWA and inner shareable */
-#define TCR_FLAGS              (TCR_TG0_64K |          \
-                               TCR_SHARED_INNER |      \
-                               TCR_ORGN_WBWA |         \
-                               TCR_IRGN_WBWA |         \
-                               TCR_T0SZ(VA_BITS))
+#define TCR_EPD1_DISABLE       (1 << 23)
 
 #define TCR_EL1_RSVD           (1 << 31)
 #define TCR_EL2_RSVD           (1 << 31 | 1 << 23)
 #define TCR_EL3_RSVD           (1 << 31 | 1 << 23)
 
 #ifndef __ASSEMBLY__
-
-void set_pgtable_section(u64 *page_table, u64 index,
-                        u64 section, u64 memory_type,
-                        u64 attribute);
-void set_pgtable_table(u64 *page_table, u64 index,
-                      u64 *table_addr);
-
 static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)
 {
        asm volatile("dsb sy");
@@ -143,5 +122,17 @@ static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr)
        }
        asm volatile("isb");
 }
+
+struct mm_region {
+       u64 virt;
+       u64 phys;
+       u64 size;
+       u64 attrs;
+};
+
+extern struct mm_region *mem_map;
+void setup_pgtables(void);
+u64 get_tcr(int el, u64 *pips, u64 *pva_bits);
 #endif
+
 #endif /* _ASM_ARMV8_MMU_H_ */