armv8: ls2040a: Add support of LS2040A SoC

[u-boot] / arch / arm / include / asm / cache.h

diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index 6d60a4a6d955d276d12a492bdcf59342882a7dc0..1f63127bdc8af38269e0ab2ab9487dc1292641b9 100644 (file)
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -11,9 +11,14 @@
 
 #include <asm/system.h>
 
+#ifndef CONFIG_ARM64
+
 /*
  * Invalidate L2 Cache using co-proc instruction
  */
+#ifdef CONFIG_SYS_THUMB_BUILD
+void invalidate_l2_cache(void);
+#else
 static inline void invalidate_l2_cache(void)
 {
        unsigned int val=0;
@@ -22,12 +27,19 @@ static inline void invalidate_l2_cache(void)
                : : "r" (val) : "cc");
        isb();
 }
+#endif
 
 void l2_cache_enable(void);
 void l2_cache_disable(void);
 void set_section_dcache(int section, enum dcache_option option);
 
+void arm_init_before_mmu(void);
+void arm_init_domains(void);
+void cpu_cache_initialization(void);
 void dram_bank_mmu_setup(int bank);
+
+#endif
+
 /*
  * The current upper bound for ARM L1 data cache line sizes is 64 bytes.  We
  * use that value for aligning DMA buffers unless the board config has specified