armv8: lsch3: Add serdes and DDR voltage setup

[u-boot] / arch / arm / include / asm / io.h

diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 6121f1ddcac49febcd6ccf2a8d834aec00c6a148..5df74728de13ceab510d4f45305b7ad189bb3065 100644 (file)
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -25,6 +25,7 @@
 #include <linux/types.h>
 #include <asm/byteorder.h>
 #include <asm/memory.h>
+#include <asm/barriers.h>
 #if 0  /* XXX###XXX */
 #include <asm/arch/hardware.h>
 #endif /* XXX###XXX */
@@ -33,35 +34,6 @@ static inline void sync(void)
 {
 }
 
-/*
- * Given a physical address and a length, return a virtual address
- * that can be used to access the memory range with the caching
- * properties specified by "flags".
- */
-#define MAP_NOCACHE    (0)
-#define MAP_WRCOMBINE  (0)
-#define MAP_WRBACK     (0)
-#define MAP_WRTHROUGH  (0)
-
-static inline void *
-map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
-{
-       return (void *)((unsigned long)paddr);
-}
-
-/*
- * Take down a mapping set up by map_physmem().
- */
-static inline void unmap_physmem(void *vaddr, unsigned long flags)
-{
-
-}
-
-static inline phys_addr_t virt_to_phys(void * vaddr)
-{
-       return (phys_addr_t)((unsigned long)vaddr);
-}
-
 /*
  * Generic virtual read/write.  Note that we don't support half-word
  * read/writes.  We define __arch_*[bl] here, and leave __arch_*w
@@ -136,8 +108,7 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen)
  * TODO: The kernel offers some more advanced versions of barriers, it might
  * have some advantages to use them instead of the simple one here.
  */
-#define mb()           asm volatile("dsb sy" : : : "memory")
-#define dmb()          __asm__ __volatile__ ("" : : : "memory")
+#define mb()           dsb()
 #define __iormb()      dmb()
 #define __iowmb()      dmb()
 
@@ -426,6 +397,7 @@ out:
 #endif /* __mem_isa */
 #endif /* __KERNEL__ */
 
+#include <asm-generic/io.h>
 #include <iotrace.h>
 
 #endif /* __ASM_ARM_IO_H */