armv8: fsl_lsch2: Add LS1046A SoC support

[u-boot] / arch / arm / include / asm / macro.h

diff --git a/arch/arm/include/asm/macro.h b/arch/arm/include/asm/macro.h
index 541b4432549bf38b8c99504b6299ee4d87559e98..9bb0efa5ff04e41a345ebc8446ab509dd2c22ae3 100644 (file)
--- a/arch/arm/include/asm/macro.h
+++ b/arch/arm/include/asm/macro.h
@@ -73,11 +73,35 @@ lr  .req    x30
        b.eq    \el1_label
 .endm
 
+/*
+ * Branch if current processor is a Cortex-A57 core.
+ */
+.macro branch_if_a57_core, xreg, a57_label
+       mrs     \xreg, midr_el1
+       lsr     \xreg, \xreg, #4
+       and     \xreg, \xreg, #0x00000FFF
+       cmp     \xreg, #0xD07           /* Cortex-A57 MPCore processor. */
+       b.eq    \a57_label
+.endm
+
+/*
+ * Branch if current processor is a Cortex-A53 core.
+ */
+.macro branch_if_a53_core, xreg, a53_label
+       mrs     \xreg, midr_el1
+       lsr     \xreg, \xreg, #4
+       and     \xreg, \xreg, #0x00000FFF
+       cmp     \xreg, #0xD03           /* Cortex-A53 MPCore processor. */
+       b.eq    \a53_label
+.endm
+
 /*
  * Branch if current processor is a slave,
  * choose processor with all zero affinity value as the master.
  */
 .macro branch_if_slave, xreg, slave_label
+#ifdef CONFIG_ARMV8_MULTIENTRY
+       /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */
        mrs     \xreg, mpidr_el1
        tst     \xreg, #0xff            /* Test Affinity 0 */
        b.ne    \slave_label
@@ -90,6 +114,7 @@ lr   .req    x30
        lsr     \xreg, \xreg, #16
        tst     \xreg, #0xff            /* Test Affinity 3 */
        b.ne    \slave_label
+#endif
 .endm
 
 /*
@@ -97,12 +122,17 @@ lr .req    x30
  * choose processor with all zero affinity value as the master.
  */
 .macro branch_if_master, xreg1, xreg2, master_label
+#ifdef CONFIG_ARMV8_MULTIENTRY
+       /* NOTE: MPIDR handling will be erroneous on multi-cluster machines */
        mrs     \xreg1, mpidr_el1
        lsr     \xreg2, \xreg1, #32
        lsl     \xreg1, \xreg1, #40
        lsr     \xreg1, \xreg1, #40
        orr     \xreg1, \xreg1, \xreg2
        cbz     \xreg1, \master_label
+#else
+       b       \master_label
+#endif
 .endm
 
 .macro armv8_switch_to_el2_m, xreg1
@@ -113,6 +143,9 @@ lr  .req    x30
        mov     \xreg1, #0x33ff
        msr     cptr_el2, \xreg1        /* Disable coprocessor traps to EL2 */
 
+       /* Initialize Generic Timers */
+       msr     cntvoff_el2, xzr
+
        /* Initialize SCTLR_EL2
         *
         * setting RES1 bits (29,28,23,22,18,16,11,5,4) to 1
@@ -193,7 +226,7 @@ lr  .req    x30
 0 :    wfi
        ldr     \wreg2, [\xreg1, GICC_AIAR]
        str     \wreg2, [\xreg1, GICC_AEOIR]
-       and     \wreg2, \wreg2, #3ff
+       and     \wreg2, \wreg2, #0x3ff
        cbnz    \wreg2, 0b
 .endm
 #endif