ARM: OMAP4+: Make control module register structure generic

[u-boot] / arch / arm / include / asm / omap_common.h

diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index eee6893d643a8cc2d793bfc870667878be3e7691..2115687ad71baa3f2513aaa83fadfa696f96a24c 100644 (file)
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -326,6 +326,94 @@ struct prcm_regs {
        u32 prm_vc_cfg_channel;
 };
 
+struct omap_sys_ctrl_regs {
+       u32 control_status;
+       u32 control_id_code;
+       u32 control_std_fuse_opp_bgap;
+       u32 control_ldosram_iva_voltage_ctrl;
+       u32 control_ldosram_mpu_voltage_ctrl;
+       u32 control_ldosram_core_voltage_ctrl;
+       u32 control_paconf_global;
+       u32 control_paconf_mode;
+       u32 control_smart1io_padconf_0;
+       u32 control_smart1io_padconf_1;
+       u32 control_smart1io_padconf_2;
+       u32 control_smart2io_padconf_0;
+       u32 control_smart2io_padconf_1;
+       u32 control_smart2io_padconf_2;
+       u32 control_smart3io_padconf_0;
+       u32 control_smart3io_padconf_1;
+       u32 control_pbias;
+       u32 control_i2c_0;
+       u32 control_camera_rx;
+       u32 control_hdmi_tx_phy;
+       u32 control_uniportm;
+       u32 control_dsiphy;
+       u32 control_mcbsplp;
+       u32 control_usb2phycore;
+       u32 control_hdmi_1;
+       u32 control_hsi;
+       u32 control_ddr3ch1_0;
+       u32 control_ddr3ch2_0;
+       u32 control_ddrch1_0;
+       u32 control_ddrch1_1;
+       u32 control_ddrch2_0;
+       u32 control_ddrch2_1;
+       u32 control_lpddr2ch1_0;
+       u32 control_lpddr2ch1_1;
+       u32 control_ddrio_0;
+       u32 control_ddrio_1;
+       u32 control_ddrio_2;
+       u32 control_lpddr2io1_0;
+       u32 control_lpddr2io1_1;
+       u32 control_lpddr2io1_2;
+       u32 control_lpddr2io1_3;
+       u32 control_lpddr2io2_0;
+       u32 control_lpddr2io2_1;
+       u32 control_lpddr2io2_2;
+       u32 control_lpddr2io2_3;
+       u32 control_hyst_1;
+       u32 control_usbb_hsic_control;
+       u32 control_c2c;
+       u32 control_core_control_spare_rw;
+       u32 control_core_control_spare_r;
+       u32 control_core_control_spare_r_c0;
+       u32 control_srcomp_north_side;
+       u32 control_srcomp_south_side;
+       u32 control_srcomp_east_side;
+       u32 control_srcomp_west_side;
+       u32 control_srcomp_code_latch;
+       u32 control_pbiaslite;
+       u32 control_port_emif1_sdram_config;
+       u32 control_port_emif1_lpddr2_nvm_config;
+       u32 control_port_emif2_sdram_config;
+       u32 control_emif1_sdram_config_ext;
+       u32 control_emif2_sdram_config_ext;
+       u32 control_smart1nopmio_padconf_0;
+       u32 control_smart1nopmio_padconf_1;
+       u32 control_padconf_mode;
+       u32 control_xtal_oscillator;
+       u32 control_i2c_2;
+       u32 control_ckobuffer;
+       u32 control_wkup_control_spare_rw;
+       u32 control_wkup_control_spare_r;
+       u32 control_wkup_control_spare_r_c0;
+       u32 control_srcomp_east_side_wkup;
+       u32 control_efuse_1;
+       u32 control_efuse_2;
+       u32 control_efuse_3;
+       u32 control_efuse_4;
+       u32 control_efuse_5;
+       u32 control_efuse_6;
+       u32 control_efuse_7;
+       u32 control_efuse_8;
+       u32 control_efuse_9;
+       u32 control_efuse_10;
+       u32 control_efuse_11;
+       u32 control_efuse_12;
+       u32 control_efuse_13;
+};
+
 struct dpll_params {
        u32 m;
        u32 n;
@@ -390,6 +478,9 @@ extern struct prcm_regs const omap4_prcm;
 extern struct dplls const **dplls_data;
 extern struct vcores_data const **omap_vcores;
 extern const u32 sys_clk_array[8];
+extern struct omap_sys_ctrl_regs const **ctrl;
+extern struct omap_sys_ctrl_regs const omap4_ctrl;
+extern struct omap_sys_ctrl_regs const omap5_ctrl;
 
 void hw_data_init(void);