u32 ctrl_core_sma_sw_1;
};
+#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX)
struct dpll_params {
u32 m;
u32 n;
u32 cm_div_h23_dpll;
u32 cm_div_h24_dpll;
};
+#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */
struct dplls {
const struct dpll_params *mpu;
int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data);
};
+#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX)
enum {
OPP_LOW,
OPP_NOM,
struct volts eve;
struct volts iva;
};
+#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */
extern struct prcm_regs const **prcm;
extern struct prcm_regs const omap5_es1_prcm;
extern struct prcm_regs const dra7xx_prcm;
extern struct dplls const **dplls_data;
extern struct dplls dra7xx_dplls;
+extern struct dplls dra72x_dplls;
extern struct vcores_data const **omap_vcores;
extern const u32 sys_clk_array[8];
extern struct omap_sys_ctrl_regs const **ctrl;
+extern struct omap_sys_ctrl_regs const am33xx_ctrl;
+extern struct omap_sys_ctrl_regs const omap3_ctrl;
extern struct omap_sys_ctrl_regs const omap4_ctrl;
extern struct omap_sys_ctrl_regs const omap5_ctrl;
extern struct omap_sys_ctrl_regs const dra7xx_ctrl;
extern struct pmic_data tps659038;
extern struct pmic_data lp8733;
+extern struct pmic_data lp87565;
void hw_data_init(void);
const struct dpll_params *get_usb_dpll_params(struct dplls const *);
const struct dpll_params *get_abe_dpll_params(struct dplls const *);
+#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX)
void do_enable_clocks(u32 const *clk_domains,
u32 const *clk_modules_hw_auto,
u32 const *clk_modules_explicit_en,
void do_disable_clocks(u32 const *clk_domains,
u32 const *clk_modules_disable,
u8 wait_for_disable);
+#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */
void setup_post_dividers(u32 const base,
const struct dpll_params *params);
void enable_usb_clocks(int index);
void disable_usb_clocks(int index);
+#if defined(CONFIG_OMAP44XX) || defined(CONFIG_OMAP54XX)
void scale_vcores(struct vcores_data const *);
+#endif /* CONFIG_OMAP44XX || CONFIG_OMAP54XX */
int get_voltrail_opp(int rail_offset);
u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
u32 txdone, u32 txdone_mask, u32 opp);
s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb);
+struct tag_serialnr;
+
void omap_die_id_serial(void);
void omap_die_id_get_board_serial(struct tag_serialnr *serialnr);
void omap_die_id_usbethaddr(void);
void omap_die_id_display(void);
+#ifdef CONFIG_FASTBOOT_FLASH
+void omap_set_fastboot_vars(void);
+#else
+static inline void omap_set_fastboot_vars(void) { }
+#endif
+
void recalibrate_iodelay(void);
void omap_smc1(u32 service, u32 val);
/* Initialize general purpose I2C(0) on the SoC */
void gpi2c_init(void);
+/* Common FDT Fixups */
+int ft_hs_disable_rng(void *fdt, bd_t *bd);
+int ft_hs_fixup_dram(void *fdt, bd_t *bd);
+int ft_hs_add_tee(void *fdt, bd_t *bd);
+
/* ABB */
#define OMAP_ABB_NOMINAL_OPP 0
#define OMAP_ABB_FAST_OPP 1
#define DRA7XX 0x07000000
#define DRA72X 0x07200000
+#define DRA76X 0x07600000
static inline u8 is_dra7xx(void)
{
extern u32 *const omap_si_rev;
return (*omap_si_rev & 0xFFF00000) == DRA72X;
}
+
+static inline u8 is_dra76x(void)
+{
+ extern u32 *const omap_si_rev;
+ return (*omap_si_rev & 0xFFF00000) == DRA76X;
+}
#endif
/*
#define OMAP5432_ES2_0 0x54320200
/* DRA7XX */
+#define DRA762_ES1_0 0x07620100
#define DRA752_ES1_0 0x07520100
#define DRA752_ES1_1 0x07520110
#define DRA752_ES2_0 0x07520200
#define DRA722_ES1_0 0x07220100
#define DRA722_ES2_0 0x07220200
+#define DRA722_ES2_1 0x07220210
/*
* silicon device type
* Moving to common from cpu.h, since it is shared by various omap devices
*/
-#define DEVICE_MASK (BIT(8) | BIT(9) | BIT(10))
#define TST_DEVICE 0x0
#define EMU_DEVICE 0x1
#define HS_DEVICE 0x2