u32 cm_ssc_modfreqdiv_dpll_unipro;
u32 cm_coreaon_usb_phy1_core_clkctrl;
u32 cm_coreaon_usb_phy2_core_clkctrl;
+ u32 cm_coreaon_l3init_60m_gfclk_clkctrl;
/* cm2.core */
u32 cm_coreaon_bandgap_clkctrl;
u32 cm_l3init_ocp2scp1_clkctrl;
u32 cm_l3init_ocp2scp3_clkctrl;
u32 cm_l3init_usb_otg_ss1_clkctrl;
+ u32 cm_l3init_usb_otg_ss2_clkctrl;
u32 prm_irqstatus_mpu_2;
u32 control_padconf_wkup_base;
u32 iodelay_config_base;
u32 ctrl_core_sma_sw_0;
+ u32 ctrl_core_sma_sw_1;
};
struct dpll_params {
u32 get_sys_clk_index(void);
void enable_basic_clocks(void);
void enable_basic_uboot_clocks(void);
+
+void enable_usb_clocks(int index);
+void disable_usb_clocks(int index);
+
void scale_vcores(struct vcores_data const *);
u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
/* DRA7XX */
#define DRA752_ES1_0 0x07520100
#define DRA752_ES1_1 0x07520110
+#define DRA752_ES2_0 0x07520200
#define DRA722_ES1_0 0x07220100
/*