ehci-pci: Prepare for usage of readl()/writel() accessors

[u-boot] / arch / arm / include / asm / omap_common.h

diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index 605c549f0a5a647b84874d7cd4ed108762c63cc5..c1a70b15d02ecad1846688ce4af0da3cd1fc558e 100644 (file)
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -539,18 +539,26 @@ struct pmic_data {
        int (*pmic_write)(u8 sa, u8 reg_addr, u8 reg_data);
 };
 
+enum {
+       OPP_LOW,
+       OPP_NOM,
+       OPP_OD,
+       OPP_HIGH,
+       NUM_OPPS,
+};
+
 /**
  * struct volts_efuse_data - efuse definition for voltage
  * @reg:       register address for efuse
  * @reg_bits:  Number of bits in a register address, mandatory.
  */
 struct volts_efuse_data {
-       u32 reg;
+       u32 reg[NUM_OPPS];
        u8 reg_bits;
 };
 
 struct volts {
-       u32 value;
+       u32 value[NUM_OPPS];
        u32 addr;
        struct volts_efuse_data efuse;
        struct pmic_data *pmic;
@@ -558,6 +566,16 @@ struct volts {
        u32 abb_tx_done_mask;
 };
 
+enum {
+       VOLT_MPU,
+       VOLT_CORE,
+       VOLT_MM,
+       VOLT_GPU,
+       VOLT_EVE,
+       VOLT_IVA,
+       NUM_VOLT_RAILS,
+};
+
 struct vcores_data {
        struct volts mpu;
        struct volts core;
@@ -582,6 +600,7 @@ extern struct omap_sys_ctrl_regs const omap5_ctrl;
 extern struct omap_sys_ctrl_regs const dra7xx_ctrl;
 
 extern struct pmic_data tps659038;
+extern struct pmic_data lp8733;
 
 void hw_data_init(void);
 
@@ -612,6 +631,7 @@ void enable_usb_clocks(int index);
 void disable_usb_clocks(int index);
 
 void scale_vcores(struct vcores_data const *);
+int get_voltrail_opp(int rail_offset);
 u32 get_offset_code(u32 volt_offset, struct pmic_data *pmic);
 void do_scale_vcore(u32 vcore_reg, u32 volt_mv, struct pmic_data *pmic);
 void abb_setup(u32 fuse, u32 ldovbb, u32 setup, u32 control,
@@ -632,6 +652,7 @@ void omap_smc1(u32 service, u32 val);
  * security (HS) device variants by doing a specially-formed smc entry.
  */
 u32 omap_smc_sec(u32 service, u32 proc_id, u32 flag, u32 *params);
+u32 omap_smc_sec_cpu1(u32 service, u32 proc_id, u32 flag, u32 *params);
 
 void enable_edma3_clocks(void);
 void disable_edma3_clocks(void);
@@ -746,9 +767,11 @@ static inline u8 is_dra72x(void)
 #define OMAP_SRAM_SCRATCH_VCORES_PTR    (SRAM_SCRATCH_SPACE_ADDR + 0x1C)
 #define OMAP_SRAM_SCRATCH_SYS_CTRL     (SRAM_SCRATCH_SPACE_ADDR + 0x20)
 #define OMAP_SRAM_SCRATCH_BOOT_PARAMS  (SRAM_SCRATCH_SPACE_ADDR + 0x24)
-#define OMAP_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR + 0x28)
-#define OMAP_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200)
-#define OMAP_SRAM_SCRATCH_SPACE_END    (OMAP_SRAM_SCRATCH_BOARD_EEPROM_END)
+#ifndef TI_SRAM_SCRATCH_BOARD_EEPROM_START
+#define TI_SRAM_SCRATCH_BOARD_EEPROM_START (SRAM_SCRATCH_SPACE_ADDR + 0x28)
+#define TI_SRAM_SCRATCH_BOARD_EEPROM_END (SRAM_SCRATCH_SPACE_ADDR + 0x200)
+#endif
+#define OMAP_SRAM_SCRATCH_SPACE_END    (TI_SRAM_SCRATCH_BOARD_EEPROM_END)
 
 /* Boot parameters */
 #define DEVICE_DATA_OFFSET     0x18