arm: imx: hab: Define HAB_RVT_BASE according to the processor version

[u-boot] / arch / arm / include / asm / omap_mmc.h

diff --git a/arch/arm/include/asm/omap_mmc.h b/arch/arm/include/asm/omap_mmc.h
index 297e6a73802f27b156d699d72dfbc9ce829da5be..bf9de9b21151c50e56c3450aa0cfc2357285d47a 100644 (file)
--- a/arch/arm/include/asm/omap_mmc.h
+++ b/arch/arm/include/asm/omap_mmc.h
@@ -28,8 +28,11 @@
 #include <mmc.h>
 
 struct hsmmc {
-#ifdef CONFIG_DM_MMC
-       unsigned char res0[0x100];
+#ifndef CONFIG_OMAP34XX
+       unsigned int hl_rev;
+       unsigned int hl_hwinfo;
+       unsigned int hl_sysconfig;
+       unsigned char res0[0xf4];
 #endif
        unsigned char res1[0x10];
        unsigned int sysconfig;         /* 0x10 */
@@ -52,6 +55,9 @@ struct hsmmc {
        unsigned int ie;                /* 0x134 */
        unsigned char res4[0x8];
        unsigned int capa;              /* 0x140 */
+       unsigned char res5[0x10];
+       unsigned int admaes;            /* 0x154 */
+       unsigned int admasal;           /* 0x158 */
 };
 
 struct omap_hsmmc_plat {
@@ -64,6 +70,7 @@ struct omap_hsmmc_plat {
 /*
  * OMAP HS MMC Bit definitions
  */
+#define MADMA_EN                       (0x1 << 0)
 #define MMC_SOFTRESET                  (0x1 << 1)
 #define RESETDONE                      (0x1 << 0)
 #define NOOPENDRAIN                    (0x0 << 0)
@@ -80,12 +87,12 @@ struct omap_hsmmc_plat {
 #define WPP_ACTIVEHIGH                 (0x0 << 8)
 #define RESERVED_MASK                  (0x3 << 9)
 #define CTPL_MMC_SD                    (0x0 << 11)
+#define DMA_MASTER                     (0x1 << 20)
 #define BLEN_512BYTESLEN               (0x200 << 0)
 #define NBLK_STPCNT                    (0x0 << 16)
-#define DE_DISABLE                     (0x0 << 0)
-#define BCE_DISABLE                    (0x0 << 1)
+#define DE_ENABLE                      (0x1 << 0)
 #define BCE_ENABLE                     (0x1 << 1)
-#define ACEN_DISABLE                   (0x0 << 2)
+#define ACEN_ENABLE                    (0x1 << 2)
 #define DDIR_OFFSET                    (4)
 #define DDIR_MASK                      (0x1 << 4)
 #define DDIR_WRITE                     (0x0 << 4)
@@ -119,13 +126,13 @@ struct omap_hsmmc_plat {
 #define SDBP_PWRON                     (0x1 << 8)
 #define SDVS_1V8                       (0x5 << 9)
 #define SDVS_3V0                       (0x6 << 9)
+#define DMA_SELECT                     (0x2 << 3)
 #define ICE_MASK                       (0x1 << 0)
 #define ICE_STOP                       (0x0 << 0)
 #define ICS_MASK                       (0x1 << 1)
 #define ICS_NOTREADY                   (0x0 << 1)
 #define ICE_OSCILLATE                  (0x1 << 0)
 #define CEN_MASK                       (0x1 << 2)
-#define CEN_DISABLE                    (0x0 << 2)
 #define CEN_ENABLE                     (0x1 << 2)
 #define CLKD_OFFSET                    (6)
 #define CLKD_MASK                      (0x3FF << 6)
@@ -148,6 +155,7 @@ struct omap_hsmmc_plat {
 #define IE_DTO                         (0x01 << 20)
 #define IE_DCRC                                (0x01 << 21)
 #define IE_DEB                         (0x01 << 22)
+#define IE_ADMAE                       (0x01 << 25)
 #define IE_CERR                                (0x01 << 28)
 #define IE_BADA                                (0x01 << 29)