armv8: ls2040a: Add support of LS2040A SoC

[u-boot] / arch / arm / include / asm / system.h

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 9cd2f1e592c566863e9733ebfed7876d0ac8de8d..67cbbc261066e1e5547ac05a080a4a5f49ff3969 100644 (file)
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -1,6 +1,9 @@
 #ifndef __ASM_ARM_SYSTEM_H
 #define __ASM_ARM_SYSTEM_H
 
+#include <common.h>
+#include <linux/compiler.h>
+
 #ifdef CONFIG_ARM64
 
 /*
@@ -14,10 +17,22 @@
 #define CR_WXN         (1 << 19)       /* Write Permision Imply XN     */
 #define CR_EE          (1 << 25)       /* Exception (Big) Endian       */
 
+#ifndef CONFIG_SYS_FULL_VA
 #define PGTABLE_SIZE   (0x10000)
+#else
+#define PGTABLE_SIZE   CONFIG_SYS_PGTABLE_SIZE
+#endif
+
+/* 2MB granularity */
+#define MMU_SECTION_SHIFT      21
+#define MMU_SECTION_SIZE       (1 << MMU_SECTION_SHIFT)
 
 #ifndef __ASSEMBLY__
 
+enum dcache_option {
+       DCACHE_OFF = 0x3,
+};
+
 #define isb()                          \
        ({asm volatile(                 \
        "isb" : : : "memory");          \
@@ -65,6 +80,17 @@ static inline void set_sctlr(unsigned int val)
        asm volatile("isb");
 }
 
+static inline unsigned long read_mpidr(void)
+{
+       unsigned long val;
+
+       asm volatile("mrs %0, mpidr_el1" : "=r" (val));
+
+       return val;
+}
+
+#define BSP_COREID     0
+
 void __asm_flush_dcache_all(void);
 void __asm_invalidate_dcache_all(void);
 void __asm_flush_dcache_range(u64 start, u64 end);
@@ -77,10 +103,29 @@ void armv8_switch_to_el1(void);
 void gic_init(void);
 void gic_send_sgi(unsigned long sgino);
 void wait_for_wakeup(void);
+void protect_secure_region(void);
 void smp_kick_all_cpus(void);
 
 void flush_l3_cache(void);
 
+/*
+ *Issue a hypervisor call in accordance with ARM "SMC Calling convention",
+ * DEN0028A
+ *
+ * @args: input and output arguments
+ *
+ */
+void hvc_call(struct pt_regs *args);
+
+/*
+ *Issue a secure monitor call in accordance with ARM "SMC Calling convention",
+ * DEN0028A
+ *
+ * @args: input and output arguments
+ *
+ */
+void smc_call(struct pt_regs *args);
+
 #endif /* __ASSEMBLY__ */
 
 #else /* CONFIG_ARM64 */
@@ -129,7 +174,9 @@ void flush_l3_cache(void);
 #define CR_AFE (1 << 29)       /* Access flag enable                   */
 #define CR_TE  (1 << 30)       /* Thumb exception enable               */
 
+#ifndef PGTABLE_SIZE
 #define PGTABLE_SIZE           (4096 * 4)
+#endif
 
 /*
  * This is used to ensure the compiler did actually allocate the register we
@@ -158,6 +205,22 @@ void flush_l3_cache(void);
  * void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3);
  */
 
+/**
+ * save_boot_params_ret() - Return from save_boot_params()
+ *
+ * If you provide save_boot_params(), then you should jump back to this
+ * function when done. Try to preserve all registers.
+ *
+ * If your implementation of save_boot_params() is in C then it is acceptable
+ * to simply call save_boot_params_ret() at the end of your function. Since
+ * there is no link register set up, you cannot just exit the function. U-Boot
+ * will return to the (initialised) value of lr, and likely crash/hang.
+ *
+ * If your implementation of save_boot_params() is in assembler then you
+ * should use 'b' or 'bx' to return to save_boot_params_ret.
+ */
+void save_boot_params_ret(void);
+
 #define isb() __asm__ __volatile__ ("" : : : "memory")
 
 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
@@ -171,7 +234,7 @@ void flush_l3_cache(void);
 static inline unsigned int get_cr(void)
 {
        unsigned int val;
-       asm("mrc p15, 0, %0, c1, c0, 0  @ get CR" : "=r" (val) : : "cc");
+       asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
        return val;
 }
 
@@ -247,6 +310,23 @@ enum {
 #define TTBR0_IRGN_WB                  (1 << 0 | 1 << 6)
 #endif
 
+/**
+ * Register an update to the page tables, and flush the TLB
+ *
+ * \param start                start address of update in page table
+ * \param stop         stop address of update in page table
+ */
+void mmu_page_table_flush(unsigned long start, unsigned long stop);
+
+#endif /* __ASSEMBLY__ */
+
+#define arch_align_stack(x) (x)
+
+#endif /* __KERNEL__ */
+
+#endif /* CONFIG_ARM64 */
+
+#ifndef __ASSEMBLY__
 /**
  * Change the cache settings for a region.
  *
@@ -257,14 +337,6 @@ enum {
 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
                                     enum dcache_option option);
 
-/**
- * Register an update to the page tables, and flush the TLB
- *
- * \param start                start address of update in page table
- * \param stop         stop address of update in page table
- */
-void mmu_page_table_flush(unsigned long start, unsigned long stop);
-
 #ifdef CONFIG_SYS_NONCACHED_MEMORY
 void noncached_init(void);
 phys_addr_t noncached_alloc(size_t size, size_t align);
@@ -272,10 +344,4 @@ phys_addr_t noncached_alloc(size_t size, size_t align);
 
 #endif /* __ASSEMBLY__ */
 
-#define arch_align_stack(x) (x)
-
-#endif /* __KERNEL__ */
-
-#endif /* CONFIG_ARM64 */
-
 #endif