#define CR_EE (1 << 25) /* Exception (Big) Endian */
#define PGTABLE_SIZE (0x10000)
+/* 2MB granularity */
+#define MMU_SECTION_SHIFT 21
+#define MMU_SECTION_SIZE (1 << MMU_SECTION_SHIFT)
#ifndef __ASSEMBLY__
+enum dcache_option {
+ DCACHE_OFF = 0x3,
+};
+
#define isb() \
({asm volatile( \
"isb" : : : "memory"); \
static inline unsigned int get_cr(void)
{
unsigned int val;
- asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
+ asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
return val;
}
#define TTBR0_IRGN_WB (1 << 0 | 1 << 6)
#endif
+/**
+ * Register an update to the page tables, and flush the TLB
+ *
+ * \param start start address of update in page table
+ * \param stop stop address of update in page table
+ */
+void mmu_page_table_flush(unsigned long start, unsigned long stop);
+
+#endif /* __ASSEMBLY__ */
+
+#define arch_align_stack(x) (x)
+
+#endif /* __KERNEL__ */
+
+#endif /* CONFIG_ARM64 */
+
+#ifndef __ASSEMBLY__
/**
* Change the cache settings for a region.
*
void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
enum dcache_option option);
-/**
- * Register an update to the page tables, and flush the TLB
- *
- * \param start start address of update in page table
- * \param stop stop address of update in page table
- */
-void mmu_page_table_flush(unsigned long start, unsigned long stop);
-
#ifdef CONFIG_SYS_NONCACHED_MEMORY
void noncached_init(void);
phys_addr_t noncached_alloc(size_t size, size_t align);
#endif /* __ASSEMBLY__ */
-#define arch_align_stack(x) (x)
-
-#endif /* __KERNEL__ */
-
-#endif /* CONFIG_ARM64 */
-
#endif