tegra124: Reserve secure RAM using MC_SECURITY_CFG{0, 1}_0

[u-boot] / arch / arm / include / asm / system.h

diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 2a5bed2e46b67b7adacddc1ed43a395e34c3d9f8..fe103352fce6400b392c87e8b92873ab5179133e 100644 (file)
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -77,6 +77,7 @@ void armv8_switch_to_el1(void);
 void gic_init(void);
 void gic_send_sgi(unsigned long sgino);
 void wait_for_wakeup(void);
+void protect_secure_region(void);
 void smp_kick_all_cpus(void);
 
 void flush_l3_cache(void);
@@ -196,6 +197,28 @@ static inline void set_dacr(unsigned int val)
        isb();
 }
 
+#ifdef CONFIG_ARMV7
+/* Short-Descriptor Translation Table Level 1 Bits */
+#define TTB_SECT_NS_MASK       (1 << 19)
+#define TTB_SECT_NG_MASK       (1 << 17)
+#define TTB_SECT_S_MASK                (1 << 16)
+/* Note: TTB AP bits are set elsewhere */
+#define TTB_SECT_TEX(x)                ((x & 0x7) << 12)
+#define TTB_SECT_DOMAIN(x)     ((x & 0xf) << 5)
+#define TTB_SECT_XN_MASK       (1 << 4)
+#define TTB_SECT_C_MASK                (1 << 3)
+#define TTB_SECT_B_MASK                (1 << 2)
+#define TTB_SECT                       (2 << 0)
+
+/* options available for data cache on each page */
+enum dcache_option {
+       DCACHE_OFF = TTB_SECT_S_MASK | TTB_SECT_DOMAIN(0) |
+                                       TTB_SECT_XN_MASK | TTB_SECT,
+       DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK,
+       DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK,
+       DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),
+};
+#else
 /* options available for data cache on each page */
 enum dcache_option {
        DCACHE_OFF = 0x12,
@@ -203,6 +226,7 @@ enum dcache_option {
        DCACHE_WRITEBACK = 0x1e,
        DCACHE_WRITEALLOC = 0x16,
 };
+#endif
 
 /* Size of an MMU section */
 enum {
@@ -210,6 +234,20 @@ enum {
        MMU_SECTION_SIZE        = 1 << MMU_SECTION_SHIFT,
 };
 
+#ifdef CONFIG_ARMV7
+/* TTBR0 bits */
+#define TTBR0_BASE_ADDR_MASK   0xFFFFC000
+#define TTBR0_RGN_NC                   (0 << 3)
+#define TTBR0_RGN_WBWA                 (1 << 3)
+#define TTBR0_RGN_WT                   (2 << 3)
+#define TTBR0_RGN_WB                   (3 << 3)
+/* TTBR0[6] is IRGN[0] and TTBR[0] is IRGN[1] */
+#define TTBR0_IRGN_NC                  (0 << 0 | 0 << 6)
+#define TTBR0_IRGN_WBWA                        (0 << 0 | 1 << 6)
+#define TTBR0_IRGN_WT                  (1 << 0 | 0 << 6)
+#define TTBR0_IRGN_WB                  (1 << 0 | 1 << 6)
+#endif
+
 /**
  * Change the cache settings for a region.
  *